High-density nonvolatile semiconductor memory

Claim 2

A nonvolatile semiconductor memory device having a plurality of memory cells, each of said memory cells having a floating gate, a control gate, a source and a drain, said device comprising: a semiconductor substrate: a plurality of active regions formed in said semiconductor substrate as parallel strips extending in a first direction and arranged separately from one another, each of said active regions having said sources, said drains, and having channels which are arranged between said sources and said drains; said plurality of floating gates being formed over respective channels; a plurality of control gate lines extending in a second direction different from said first direction, each of said control gate lines having said plurality of control gates formed over respective floating gates; a plurality of insulating films covering upper surface of respective control gate lines and sides of respective control gate lines and floating gates; and a plurality of source interconnecting lines formed on said semiconductor substrate and a portion of said insulating films as parallel strips of a conductive material, extending in said second direction, for interconnecting said sources arranged in different active regions.

Claim 3

The memory device of claim 1, wherein said first direction and said second direction are mutually perpendicular.

Claim 4

The memory device of claim 1, wherein said source interconnecting lines comprise a refractory metal.

Claim 5

The memory device of claim 3, wherein said source interconnecting lines comprise tungsten.

Claim 6

The memory device of claim 1, further comprising: a plurality of pads formed of a conductive material on respective drains; and a plurality of bit lines formed as parallel strips extending in said first direction, making contact with said pads arranged in the same active regions.

Claim 7

The memory device of claim 5, wherein said pads comprise a conductive material identical to the conductive material of said source interconnecting lines.

Claim 8

A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a first active region formed in said semiconductor substrate extending in a first direction, said first active region having a first source, a first drain, a second drain, a first channel and a second channel, wherein said first channel is formed between said first source and said first drain and said second channel is formed between said first source and said second drain; a second active region formed in said semiconductor substrate extending in said first direction, said first and second active regions being formed separately from each other, said second active region having a second source, a third drain, a fourth drain, a third channel and a fourth channel, wherein said third channel is formed between said second source and said third drain, and said fourth channel is formed between said second source and said fourth drain; first to fourth floating gates respectively formed over said first to fourth channels; a first control gate line extending in a second direction from said first direction, said first control gate line including a first control gate formed over said first floating gate and a second control gate formed over said third floating gate; a second control gate line extending in said second direction, said second control gate line including a third control gate formed over said second floating gate and a fourth control gate formed over said fourth floating gate; an insulating film covering upper surfaces of said first and second control gate lines and sides of said first and second control gate lines and said first to fourth floating gates; a source interconnecting line formed on said semiconductor substrate and a portion of said insulating film for interconnecting said first and second sources; a first drain interconnecting line formed over said first active region for interconnecting said first and second drains; and a second drain interconnecting line formed over said second active region for interconnecting said third and fourth drains.

Claim 9

A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a first active region formed in said semiconductor substrate extending in a first direction, said first active region having a first source, a first drain, a second drain, a first channel and a second channel, wherein said first channel is formed between said first source and said first drain and said second channel is formed between said first source and said second drain; a second active region formed in said semiconductor substrate extending in said first direction, said first and second active regions being formed separately from each other, said second active region having a second source, a third drain, a fourth drain, a third channel and a fourth channel, wherein said third channel is formed between said second source and said third drain, and said fourth channel is formed between said second source and said fourth drain; first to fourth floating gates respectively formed over said first to fourth channels; a first control gate line extending in a second direction from said first direction, said first control gate line including a first control gate formed over said first floating gate and a second control gate formed over said third floating gate; a second control gate line extending in said second direction, said second control gate line including a third control gate formed over said second floating gate and a fourth control gate formed over said fourth floating gate; an insulating film covering upper surfaces of said first and second control gate lines and sides of said first and second control gate lines and said first to fourth floating gates; a source interconnecting line formed on said semiconductor substrate and a portion of said insulating film for interconnecting said first and second sources; a first drain interconnecting line formed over said first active region for interconnecting said first and second drains; and a second drain interconnecting line formed over said second active region for interconnecting said third and fourth drains.

Claim 10

The memory device of claim 7, wherein said first direction and said second direction are mutually perpendicular.

Claim 11

The memory device of claim 7, wherein said source interconnecting lines comprise a refractory metal.

Claim 12

The memory device of claim 9, wherein said source interconnecting lines comprise tungsten.

Claim 13

The memory device of claim 7, wherein said first source is provided in common for said first and third control gates and said second source is provided in common for said second and fourth control gate.

Claim 14

The memory device of claim 7, further comprising: a first pad disposed between said first drain and said first drain interconnecting line; a second pad disposed between said second drain and said first drain interconnecting line; a third pad disposed between said third drain and said second drain interconnecting lines; and a fourth pad disposed between said fourth drain and said second drain interconnecting line.