EP0502438A2
Expired / Lapsed
EP
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Non-volatile memory, semiconductor memory device having the non-volatile memory, and method of producing the semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1992-02-28
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Granted: —
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Expires: 2012-02-28
Abstract
Abstract A non-volatile memory device includes a semiconductor layer (1), floating gates (12), control gates (14), pairs of first and second impurity diffused layers (15, 16) formed in the semiconductor layer and located on both sides of the control gates. Word lines (14) are electrically connected to the control gates, and bit lines (17) are electrically connected to the first impurity diffused layers and perpendicular to the word lines. Wiring electrodes (18) are electrically connected to the second impurity diffused layers, and run in a direction in which the bit lines run. Areas (X) including the pairs of first and second impurity diffused areas are obliquely arranged with respect to the bit lines.
Inventors
- 👤 Taiji C/O Fujitsu Limited Ema
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 12:31
CPC Classifications
H; H10; H10B; H10B69/00; H10B41/00; H10B41/30
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
148 words
A non-volatile memory device characterized by comprising: a semiconductor layer (1); floating gates (12) formed on a first insulating film formed on said semiconductor layer; control gates (14) which are respectively formed on a second insulating film formed on the first insulating film and which are respectively located above said floating gates; pairs of first and second impurity diffused layers (15, 16) formed in said semiconductor layer and located on both sides of said control gates; word lines (14) electrically connected to said control gates; bit lines (17) electrically connected to the first impurity diffused layers and perpendicular to said word lines; wiring electrodes (18) electrically connected to the second impurity diffused layers, said wiring electrodes running in a direction in which said bit lines run, wherein areas (X) including said pairs of first and second impurity diffused areas are obliquely arranged with respect to said bit lines.
Claim 2
Dependent Claim
23 words
A non-volatile memory device as claimed in claim 1, characterized in that said areas are zigzag arranged with respect to said bit lines.
Claim 3
Dependent Claim
29 words
A non-volatile memory device as claimed in claim 1 or 2, characterized in that each of said wiring electrodes and said bit lines are formed on different insulator films.
Claim 4
Dependent Claim
50 words
A non-volatile memory device as claimed in claim 3, characterized in that each of said wiring electrodes has a fin-shaped structure which has at least one vertical portion connected to one of the second impurity diffused layers, and at least one fin substantially horizontally extending from said one vertical portion.
Claim 5
Dependent Claim
36 words
A non-volatile memory device as claimed in anyone of claims 2 to 4, characterized in that said bit lines are in contact with said first impurity diffused layers at corner portions of said areas arranged zigzag.
Claim 6
Dependent Claim
262 words
A semiconductor memory device characterized by comprising: a semiconductor layer (1); floating gates (12) formed on a first insulating film formed on said semiconductor layer; control gates (14) which are respectively formed on a second insulating film formed on the first insulating film and which are respectively located above said floating gates; pairs of first and second impurity diffused layers (15, 16) formed in said semiconductor layer and located on both sides of said control gates; first word lines (14) electrically connected to said control gates; first bit lines (17) electrically connected to the first impurity diffused layers and perpendicular to said word lines; wiring electrodes (18) electrically connected to the second impurity diffused layers; said control gates, said floating gates, said pairs of first and second impurity diffused layers, said first word lines, and said first bit lines forming non-volatile memory elements, said wiring electrodes running in a direction in which said first bit lines run, second word lines (22) formed on said first insulating layer; pairs of third and fourth impurity diffused layers (23, 24) formed in said semiconductor layer and located on both sides of said second word lines; second bit lines (26) electrically connected to the third impurity diffused layers; and capacitors (31, 32, 33) electrically connected to the fourth impurity diffused layers, said capacitors including storage electrodes, and said second word lines, said pairs of third and fourth impurity diffused layers, said second bit lines, and said capacitors forming volatile memory elements, said storage electrodes and said wiring electrodes are layers formed from a first conductive layer.
Claim 7
Dependent Claim
28 words
A semiconductor memory device as claimed in claim 6, characterized in that said second word lines and said control gates are layers formed from a second conductive layer.
Claim 8
Dependent Claim
31 words
A semiconductor memory device as claimed in claim 6 or 7, characterized in that said first bit lines and said second bit lines are layers formed from a third conductive layer.
Claim 9
Dependent Claim
37 words
A semiconductor memory device as claimed in anyone of claims 6 to 8, characterized in that areas including said pairs of first and second impurity diffused areas are obliquely arranged with respect to said first bit lines.
Claim 10
Dependent Claim
37 words
A semiconductor memory device as claimed in anyone of claims 6 to 9, characterized in that each of said wiring electrodes has a first fin-shaped structure, and each of said storage electrodes has a second fin-shaped structure.
Claim 11
Dependent Claim
26 words
A semiconductor memory device as claimed in claim 10, characterized in that said first fin-shaped structure has fins equal in number to said second fin-shaped structure.
Claim 12
Independent Claim
239 words
A method of producing a semiconductor memory device, characterized by comprising the steps of: a) forming floating gates (12) of non-volatile memory elements on a first insulating film (11) on a semiconductor layer; b) forming a second insulating film (13) on said floating gates; c) simultaneously forming, on said second insulating film, control gates (14) located above said floating gates, and gate electrodes (21) of volatile memory elements; d) simultaneously forming pairs of first and second impurity diffused layers (15, 16) located on both sides of said control gates serving as masks, and pairs of third and fourth impurity diffused layers (23, 24) located on both side of said gate electrodes serving as masks; e) forming a third insulating film (3) so that said third insulating film covers said control gates and said gate electrodes; f) simultaneously forming first bit lines (4) connected to said first impurity diffused layers via contact holes formed in said third insulating film, and second bit lines (26) connected to said third impurity diffused layers via contact holes formed in said third insulating film; g) simultaneously forming wiring electrodes (18) electrically connected to the second impurity diffused layers, and storage electrodes (31) of capacitors electrically connected to said fourth impurity diffused layers; h) forming dielectric films (32) around said storage electrodes; and i) forming a cell plate (33) so that said cell plate covers said storage electrodes around which said dielectric films are formed.
Claim 13
Independent Claim
126 words
A method as claimed in clam 12, characterized in that said step (g) comprises the steps of: forming a composite layer (57-59) including at least one insulating layer and at least one conductive layer so that said composite layer covers said first and second bit lines; forming first and second openings (61, 60) so that said first and second openings penetrate said first, second and third insulating layers and said composite layer; forming a conductive layer (62) on said second and fourth impurity diffused layers and around inner walls of said first and second openings; patterning said composite layer said conductive layer into predetermined shapes; removing said insulating layer (57, 59) of said composite layer, so that said storage electrodes and said wiring electrodes are formed.
References Cited (Backward Citations)
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