Patent US5400294A successfully refreshed from Google Patents.
US5400294A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory cell with user-selectable logic state on power-up
Assignee: Mentor Graphics Corp
•
Filing: 1993-12-06
•
Granted: 1995-03-21
•
Expires: 2013-12-06
Abstract
Abstract Apparatus for forcing a memory cell to a user-selected logic level upon power-up includes circuitry for providing two signals PWRUP and PWRUPB which are used during chip power-up. At power-up, as V CC rises from 0 volt to 3.5 volts, the PWRUP signal follows V CC and the PWRUPB signal maintains 0 volts. The PWRUP and PWRUPB signals are used to drive the gates of P-Channel and N-Channel MOS transistors, respectively, including pass gates connected between word line driver circuits and bit line driver circuits driving the word lines and bit lines associated with the memory cells. In addition, the PWRUPB signal is used to drive P-Channel MOS pullup transistors connected between the word lines and V CC and bit lines and V CC . During power-up, the pass gates are disabled, disconnecting the word lines and bit lines from their drivers. The word lines and bit lines are forced to follow the rise of V CC by the P-Channel pullup transistors. When V CC reaches its desired value, the PWRUP signal goes to 0 volts and the PWRUPB signal goes to V CC , thus turning on the pass gates to connect the word line and bit line driver circuits to the word lines and bit lines. The V CC final PWRUPB signal turns off the P-Channel MOS pullup transistors connected between the word lines and V CC and the bit lines and V CC .
Inventors
- 👤 Adi Srinivasan
- 👤 Ta-Pen Guo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:28
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/20; G11C7/22
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
153 words
In an integrated circuit including a user-accessible input pin to which may be applied a user-selected logic level, and a random access memory cell having an output node connectable to a bit line through a select device, said select device driven by a signal from a word line driver on a word line and said bit line driven by a bit line driver, apparatus for setting said random access memory cell to said user-selected logic level during a power-up interval of said integrated circuit while a potential difference powering said integrated circuit increases from zero volts to an operating value, said apparatus comprising: first means for disconnecting the bit line driver from the bit line during the power-up interval; second means for disconnecting the word line driver from the bit line during the power-up interval; third means for writing the user-selected logic level into the random access memory cell during the power-up interval.
Claim 2
Dependent Claim
153 words
In an integrated circuit including a user-accessible input pin to which may be applied a user-selected logic level, and a random access memory cell having an output node connectable to a bit line through a select device, said select device driven by a signal from a word line driver on a word line and said bit line driven by a bit line driver, apparatus for setting said random access memory cell to said user-selected logic level during a power-up interval of said integrated circuit while a potential difference powering said integrated circuit increases from zero volts to an operating value, said apparatus comprising: first means for disconnecting the bit line driver from the bit line during the power-up interval; second means for disconnecting the word line driver from the bit line during the power-up interval; third means for writing the user-selected logic level into the random access memory cell during the power-up interval.
Claim 3
Dependent Claim
216 words
In an integrated circuit including a user-accessible input pin to which may be applied a user-selected logic level, said integrated circuit powered by a first potential difference to ground and further including at least one random access memory cell powered by a source of a second potential difference to ground larger than said first potential difference, said at least one random access memory cell comprising a cross-coupled latch having an output node connectable to a bit line through a select device, said select device driven by a signal from a word line driver on a word line and said bit line driven by a bit line driver, apparatus for setting said at least one random access memory cell to said user-selected logic level during a power-up interval of said integrated circuit while said second potential difference increases from zero volts to an operating value, said apparatus comprising: first means for disconnecting the word line driver from the select device and for turning on the select device during the power-up interval; second means for disconnecting the bit line driver from the bit line and for connecting the second potential difference to the bit line during the power-up interval; and third means for writing the user-selected logic level into the random access memory cell during the power-up interval.
Claim 4
Dependent Claim
216 words
In an integrated circuit including a user-accessible input pin to which may be applied a user-selected logic level, said integrated circuit powered by a first potential difference to ground and further including at least one random access memory cell powered by a source of a second potential difference to ground larger than said first potential difference, said at least one random access memory cell comprising a cross-coupled latch having an output node connectable to a bit line through a select device, said select device driven by a signal from a word line driver on a word line and said bit line driven by a bit line driver, apparatus for setting said at least one random access memory cell to said user-selected logic level during a power-up interval of said integrated circuit while said second potential difference increases from zero volts to an operating value, said apparatus comprising: first means for disconnecting the word line driver from the select device and for turning on the select device during the power-up interval; second means for disconnecting the bit line driver from the bit line and for connecting the second potential difference to the bit line during the power-up interval; and third means for writing the user-selected logic level into the random access memory cell during the power-up interval.
Claim 5
Dependent Claim
158 words
In an integrated circuit including a random access memory cell and a user-accessible input pin to which may be applied a user-selected logic level, said random access memory cell having an output node connectable to a bit line through a select device, said select device driven by a signal from a word line driver on a word line and said bit line driven by a bit line driver, apparatus for setting said random access memory cell to said user-selected logic level during a power-up interval of said integrated circuit while a potential difference powering said integrated circuit increases form zero volts to an operating value, said apparatus comprising: first means for disconnecting the bit line driver from the bit line during the power-up interval; second means for disconnecting the word line driver from the bit line during the power-up interval; third means for writing the user-selected logic level into the random access memory cell during the power-up interval.
Claim 6
Dependent Claim
158 words
In an integrated circuit including a random access memory cell and a user-accessible input pin to which may be applied a user-selected logic level, said random access memory cell having an output node connectable to a bit line through a select device, said select device driven by a signal from a word line driver on a word line and said bit line driven by a bit line driver, apparatus for setting said random access memory cell to said user-selected logic level during a power-up interval of said integrated circuit while a potential difference powering said integrated circuit increases form zero volts to an operating value, said apparatus comprising: first means for disconnecting the bit line driver from the bit line during the power-up interval; second means for disconnecting the word line driver from the bit line during the power-up interval; third means for writing the user-selected logic level into the random access memory cell during the power-up interval.
Claim 7
Dependent Claim
208 words
In an integrated circuit including a user-accessible input pin to which may be applied a user-selected logic level, said integrated circuit powered by a first potential difference to ground and further including at least one random access memory cell powered by a source of a second potential difference to ground larger than said first potential difference, said at least one random access memory cell comprising a cross-coupled latch having an output node connectable to a bit line through a select device, said select device driven by a signal from a word line driver on a word line and said bit line driven by a bit line driver, apparatus for setting said at least one random access memory cell to said user-selected logic level during a power-up interval of said integrated circuit while said second potential difference increases form zero volts to an operating value, said apparatus comprising: first means for disconnecting the word line driver from the select device and for turning on the select device during the power-up interval; and second means for disconnecting the bit line driver from the bit line and for connecting a signal representing the user-selected logic level derived from the user accessible input pin to the bit line during said power-up interval.
Claim 8
Dependent Claim
208 words
In an integrated circuit including a user-accessible input pin to which may be applied a user-selected logic level, said integrated circuit powered by a first potential difference to ground and further including at least one random access memory cell powered by a source of a second potential difference to ground larger than said first potential difference, said at least one random access memory cell comprising a cross-coupled latch having an output node connectable to a bit line through a select device, said select device driven by a signal from a word line driver on a word line and said bit line driven by a bit line driver, apparatus for setting said at least one random access memory cell to said user-selected logic level during a power-up interval of said integrated circuit while said second potential difference increases form zero volts to an operating value, said apparatus comprising: first means for disconnecting the word line driver from the select device and for turning on the select device during the power-up interval; and second means for disconnecting the bit line driver from the bit line and for connecting a signal representing the user-selected logic level derived from the user accessible input pin to the bit line during said power-up interval.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-20 | 1998-09-19 | 1999-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-20 | 2002-09-19 | 2003-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-20 | 2006-09-19 | 2007-03-21 | $7700.00 | Window Closed / Lapsed |