Detector circuit for testing semiconductor memory device

Claim 2

A SRAM having a normal mode of reading and writing data from and to selected memory cells in a memory cell array, comprising: detecting means connected to an input terminal for detecting a test mode signal applied to the input terminal and outputting a detection output signal for switching the normal mode to a test mode; a row decoder, a column decoder and the memory cell array responsive to the test mode to set all the memory cells to a selected status simultaneously; a control means having a control circuit responsive to the detection output signal for outputting a control output signal; and a clock generator responsive to the detection output signal and the control output signal, for generating an output signal to sense amplifiers and write buffers to enable data applied to the input terminal to be written simultaneously in all the memory cells set to the selectable status.

Claim 3

The SRAM of claim 1, wherein the input terminal is an address input terminal.

Claim 4

The SRAM of claim 1, wherein the input terminal is an input terminal for applying a test mode signal.

Claim 5

A semiconductor memory device having a normal mode of reading and writing data from and to selected memory cells of a memory cell array, comprising: timer means for outputting an activation signal activating the selected memory cells for a predetermined time period during the normal mode of reading and writing data; and control means for switching an operation mode to a test mode in response to a test mode signal applied to an input terminal and outputting the activation signal for continuously activating the memory cells while the test mode signal is being applied regardless of the operation of the timer means.

Claim 6

A semiconductor memory device having a normal mode of reading and writing data from and to selected memory cells of a memory cell array, comprising: timer means for outputting an activation signal activating the selected memory cells for a predetermined time period during the normal mode of reading and writing data; and control means for switching an operation mode to a test mode in response to a test mode signal applied to an input terminal and outputting the activation signal for continuously activating the memory cells while the test mode signal is being applied regardless of the operation of the timer means.

Claim 7

The semiconductor memory device of claim 4, wherein said control means includes detecting means for detecting the test mode signal applied to the input terminal and outputting a mode selection signal on the basis of the detected test mode signal.

Claim 8

The semiconductor memory device of claim 5, wherein the timer means obtains a logical result of a control output signal and the mode selection signal, to output the activation signal.

Claim 9

The semiconductor memory device of claim 4, wherein the input terminal is any one of an output enable pin, a positive logic chip enable and a test mode signal application pin.

Claim 10

The semiconductor memory device of claim 5, wherein the input terminal is any one of an output enable pin, a positive logic chip enable pin and a test mode signal application pin.

Claim 11

The semiconductor memory device of claim 6, wherein the input terminal is any one of an output enable pin, a positive logic chip enable pin and a test mode signal application pin.

Claim 12

A SRAM having a normal mode of reading and writing data from and to selected memory cells in a memory cell array, which comprises: detecting means for detecting a predetermined supply voltage level and outputting a detection output signal for switching the normal mode to a test mode, the output signal being applied to a row decoder, a column decoder and the memory cell array, in order to set all of the memory cells to a selectable status simultaneously; a control means having a control circuit responsive to the detection output signal, for outputting a control output signal; a clock generator responsive to the detection output signal and the control output signal, for generating an output signal to sense amplifiers and write buffers to enable data applied to the input terminal to be written simultaneously in all the memory cells set to the selectable status.

Claim 13

A SRAM having a normal mode of reading and writing data from and to selected memory cells in a memory cell array, which comprises: detecting means for detecting a predetermined supply voltage level and outputting a detection output signal for switching the normal mode to a test mode, the output signal being applied to a row decoder, a column decoder and the memory cell array, in order to set all of the memory cells to a selectable status simultaneously; a control means having a control circuit responsive to the detection output signal, for outputting a control output signal; a clock generator responsive to the detection output signal and the control output signal, for generating an output signal to sense amplifiers and write buffers to enable data applied to the input terminal to be written simultaneously in all the memory cells set to the selectable status.

Claim 14

The SRAM of claim 10, which further comprises voltage dividing means for dividing the supply voltage.

Claim 15

The SRAM of claim 11, wherein said voltage dividing means is composed of resistance elements or active elements.

Claim 16

The SRAM of claim 10, wherein in the test mode, the output of the decoder selects all the memory cells simultaneously.

Claim 17

The SRAM of claim 11, wherein in the test mode, the output of the decoder selects all the memory cells simultaneously.

Claim 18

The SRAM of claim 12, wherein in the test mode, the output of the decoder selects all the memory cells simultaneously.

Claim 19

A semiconductor memory device having a normal mode for reading and writing data from and to selected and activated memory cells in a memory cell array for a time period predetermined by a timer means, comprising: control means for switching an operation mode to a test mode, when a supply voltage is higher than a predetermined value, and outputting an output of the timer means as an activation signal for activating the memory cell continuously when the supply voltage is higher than the predetermined value.

Claim 20

A semiconductor memory device having a normal mode for reading and writing data from and to selected and activated memory cells in a memory cell array for a time period predetermined by a timer means, comprising: control means for switching an operation mode to a test mode, when a supply voltage is higher than a predetermined value, and outputting an output of the timer means as an activation signal for activating the memory cell continuously when the supply voltage is higher than the predetermined value.

Claim 21

The semiconductor memory device of claim 16, which further comprises a detecting means for detecting whether the supply voltage is higher than the predetermined value.

Claim 22

The semiconductor memory device of claim 17, which further comprises voltage dividing means for dividing the supply voltage.

Claim 23

The semiconductor memory device of claim 18, wherein said voltage dividing means is composed of resistance elements or active elements.

Claim 24

A semiconductor memory device having a normal mode for reading and writing data from and to selected memory cells in a memory cell array, comprising: control means operative in response to a test mode signal applied to an input terminal, for switching an operation mode to a test mode, thereby simultaneously setting all the memory cells to be selected in the memory cell array into a selectable status, and writing data applied to a data input terminal to all the selected memory cells simultaneously, said control means including detecting means for detecting whether the test mode signal is applied to the input terminal, and having: first and second low resistance elements both connected in series between a high supply voltage and a low supply voltage; a third low resistance element, a switching element and a fourth low resistance element all connected in series between an input terminal and the low supply voltage; a connection circuit for connecting a junction point between said first and second low resistance elements and said switching element; and an output circuit connected to a junction point between said switching element and said fourth low resistance element.

Claim 25

A semiconductor memory device having a normal mode for reading and writing data from and to selected memory cells in a memory cell array, comprising: control means operative in response to a test mode signal applied to an input terminal, for switching an operation mode to a test mode, thereby simultaneously setting all the memory cells to be selected in the memory cell array into a selectable status, and writing data applied to a data input terminal to all the selected memory cells simultaneously, said control means including detecting means for detecting whether the test mode signal is applied to the input terminal, and having: first and second low resistance elements both connected in series between a high supply voltage and a low supply voltage; a third low resistance element, a switching element and a fourth low resistance element all connected in series between an input terminal and the low supply voltage; a connection circuit for connecting a junction point between said first and second low resistance elements and said switching element; and an output circuit connected to a junction point between said switching element and said fourth low resistance element.

Claim 26

A semiconductor memory device having a normal mode of reading and writing data from and to selected and activated memory cells in a memory cell array for a time period determined by timer means, comprising: control means, operative in response to a test mode signal applied to an input terminal, for switching an operation mode to a test mode and outputting an output of the timer means as an activation signal for activating the memory cells continuously when the test mode signal is being applied; and said control means including detecting means for detecting whether the test mode signal is applied to the input terminal and outputting a mode switching signal, the detecting means having: first and second low resistance elements both connected in series between a high supply voltage and a low supply voltage; a third low resistance element, a switching element and a fourth low resistance element, connected in series between an input terminal and the low supply voltage; a connection circuit for connecting a junction point between said first and second low resistance elements and said switching element; and an output circuit connected to a junction point between said switching element and said fourth low resistance element.

Claim 27

A semiconductor memory device having a normal mode of reading and writing data from and to selected and activated memory cells in a memory cell array for a time period determined by timer means, comprising: control means, operative in response to a test mode signal applied to an input terminal, for switching an operation mode to a test mode and outputting an output of the timer means as an activation signal for activating the memory cells continuously when the test mode signal is being applied; and said control means including detecting means for detecting whether the test mode signal is applied to the input terminal and outputting a mode switching signal, the detecting means having: first and second low resistance elements both connected in series between a high supply voltage and a low supply voltage; a third low resistance element, a switching element and a fourth low resistance element, connected in series between an input terminal and the low supply voltage; a connection circuit for connecting a junction point between said first and second low resistance elements and said switching element; and an output circuit connected to a junction point between said switching element and said fourth low resistance element.

Claim 28

The semiconductor memory device of claim 20, wherein the input terminal is an address input terminal.

Claim 29

The semiconductor memory device of claim 20, wherein the input terminal is an input terminal for applying the test mode signal.

Claim 30

The semiconductor memory device of claim 21, wherein the timer means obtains a logical result of a control output signal and the mode switching signal to output the activation signal.

Claim 31

The semiconductor memory device of claim 22, wherein the input terminal is any one of an output enable pin, a positive logic chip enable pin and a test mode signal application pin.

Claim 32

A SRAM having a normal mode of reading and writing data from and to selected memory cells in a memory cell array, which comprises: detecting means connected to an input terminal, for detecting a test mode signal applied to the input terminal and outputting a detection output signal for switching the normal mode to a test mode, thereby applying the test mode signal to a row decoder, a column decoder and the memory cell array so that all the memory cells are simultaneously set to a selectable status; and control means having a control circuit, for enabling data applied to a data input terminal to be written simultaneously in all the memory cells set to the selectable status.

Claim 33

A SRAM having a normal mode of reading and writing data from and to selected memory cells in a memory cell array, which comprises: detecting means connected to an input terminal, for detecting a test mode signal applied to the input terminal and outputting a detection output signal for switching the normal mode to a test mode, thereby applying the test mode signal to a row decoder, a column decoder and the memory cell array so that all the memory cells are simultaneously set to a selectable status; and control means having a control circuit, for enabling data applied to a data input terminal to be written simultaneously in all the memory cells set to the selectable status.

Claim 34

A SRAM having a normal mode of reading and writing data from and to selected memory cells in a memory cell array, comprising: detecting means for detecting a predetermined supply voltage level and outputting a detection output signal for switching from the normal mode to a test mode, thereby applying the output signal to a row decoder, a column decoder and the memory cell array, so that all the memory cells are simultaneously set to a selectable status; control means having a control circuit responsive to the detection output signal, for outputting a control output signal; and a clock generator responsive to the detection output signal and the control output signal, for generating an output signal to sense amplifiers and write buffers to enable data applied to the input terminal to be written simultaneously in all of the memory cells set to the selectable status.

Claim 35

A SRAM having a normal mode of reading and writing data from and to selected memory cells in a memory cell array, comprising: detecting means for detecting a predetermined supply voltage level and outputting a detection output signal for switching from the normal mode to a test mode, thereby applying the output signal to a row decoder, a column decoder and the memory cell array, so that all the memory cells are simultaneously set to a selectable status; control means having a control circuit responsive to the detection output signal, for outputting a control output signal; and a clock generator responsive to the detection output signal and the control output signal, for generating an output signal to sense amplifiers and write buffers to enable data applied to the input terminal to be written simultaneously in all of the memory cells set to the selectable status.