US5399526A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing semiconductor device by forming barrier metal layer between substrate and wiring layer
Assignee: Sony Corp
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Filing: 1992-06-24
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Granted: 1995-03-21
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Expires: 2012-06-24
Abstract
Abstract A method of manufacturing a semiconductor device which comprises steps of forming a diffusion region to a semiconductor substrate; forming silicon compound film on the diffusion region; forming a metal film on the silicon compound film to form a metal silicide film and, further forming an interlayer film; forming a barrier metal material film on the interlayer film; then patterning the barrier metal material film to obtain a barrier metal layer, subsequently; patterning the interlayer film to form a contact hole and burying a wiring material into the contact hole thereby forming a wiring.
Inventors
- 👤 Hirofumi Sumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:55
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/054; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/01125; H10W20/033; H10W20/047; H10W20/051; H10W20/052; H10W20/0526; H10W20/056; H10W20/40; H10W20/41; H10W20/425; Y; Y10; Y10S; Y10S148/00; Y10S148/105
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
132 words
A method of manufacturing a semiconductor device which comprises the steps of: forming a diffusion region in a semiconductor substrate, forming a silicon compound film on said diffusion region, forming a metal film on said silicon compound film, converting the metal film and silicon compound film into a metal silicide film, forming an insulating interlayer film on said metal silicide film, forming a barrier metal layer on said insulating interlayer film, then patterning said barrier metal layer to expose a selected portion of the insulating interlayer film, subsequently etching the exposed selected portion of said insulating interlayer film to form at least one contact hole exposing a portion of the silicide film, and depositing a wiring material into said contact hole and into contact with said silicide film to form a wiring.
Claim 2
Independent Claim
132 words
A method of manufacturing a semiconductor device which comprises the steps of: forming a diffusion region in a semiconductor substrate, forming a silicon compound film on said diffusion region, forming a metal film on said silicon compound film, converting the metal film and silicon compound film into a metal silicide film, forming an insulating interlayer film on said metal silicide film, forming a barrier metal layer on said insulating interlayer film, then patterning said barrier metal layer to expose a selected portion of the insulating interlayer film, subsequently etching the exposed selected portion of said insulating interlayer film to form at least one contact hole exposing a portion of the silicide film, and depositing a wiring material into said contact hole and into contact with said silicide film to form a wiring.
Claim 3
Dependent Claim
13 words
A method according to claim 1, wherein said device is a MOS transistor.
Claim 4
Dependent Claim
13 words
A method according to claim 1, wherein said device is a bipolar transistor.
Claim 5
Dependent Claim
39 words
A method according to claim 1, wherein the step of converting the metal film and silicon compound into a metal silicide film includes a two-step annealing process, which includes a low temperature annealing followed by a high temperature annealing.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-20 | 1998-09-19 | 1999-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-20 | 2002-09-19 | 2003-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-20 | 2006-09-19 | 2007-03-21 | $7700.00 | Window Closed / Lapsed |