US5398326A
Expired / Lapsed
US
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Method for data communication
Assignee: Maxim Integrated Products Inc
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Filing: 1993-02-19
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Granted: 1995-03-14
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Expires: 2013-02-19
Abstract
Abstract A system architecture which provides efficient data communication, over a one-wire bus, with a portable data module which does not necessarily include any accurate time delay circuit whatsoever. The time delay circuit in the module can be extremely crude. An open-collector architecture is used, with electrical relations defined to absolutely minimize the drain on the portable module's battery. A protocol has been specified so that the module never sources current to the data line of the one-wire bus, but only sinks current. The protocol includes signals for read; write-zero; write-one; and reset. Each one-bit transaction is initiated by a falling edge of a voltage signal from a host. The time delay circuit in the module defines a delay, after which (in write mode) the module tests the data state of the data line. In read mode, after a falling edge of a voltage signal from the host the module does or does not turn on a pull-down transistor, depending on the value of the bit read. Thus, the host system, after the falling edge, attempts to pull the data line high again, and then tests the potential of the data line to ascertain the value of the bit read.
Inventors
- 👤 Robert D. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 00:01
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/20; G06; G06F; G06F3/00; G06F3/01; G06F3/03; G06F3/033; G06F3/038; G06F3/0383; G06F3/048; G06F3/0487; G06F3/0489; G06F3/04897; G06K; G06K19/00; G06K19/04; G06K19/041; G06K19/047; G06K19/06; G06K19/067; G06K19/07; G06K19/0701; G06K19/0702; G06K19/0706; G06K19/0723; G06K19/077; G06K19/0772; G06K19/07735; G06K19/07743; G06K7/00; G06K7/0008; G06K7/0013; G06K7/0021; G06K7/0086; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C5/00; G11C5/005; G11C5/06; G11C5/066; G11C5/14; G11C5/141; G11C7/00; G11C7/24; G11C8/10
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
471 words
A method for data communication by serial block transfers of data on a data line between a first system and at least one second system, said serial block transfers of data having at least one data bit and said data line having at least one voltage state, comprising the steps of: (a) defining a current operating mode to be either a write mode or a read mode, so that said at least one data bit of said serial block transfers of data is transferred from said first system to said at least one second system when said current operating mode is said write mode and said at least one data bit of said serial block transfers of data is transferred from said at least one second system to said first system when said current operating mode is said read mode; (b) driving said data line toward a first voltage level by said first system and thereafter driving said data line to make a transition of said data line toward a second voltage; (c) detecting said transition of said data line toward said second voltage level by said at least one second system; (d) and when said current operating mode is said read mode, (d1) driving said data line toward said second voltage level by said at least one second system and holding said data line at said second voltage level for a first time duration, said first time duration having a first length, said first length dependent upon said at least one data bit of said serial block transfers of data and releasing said data line after said first time duration, and (d2) testing the at least one voltage state of said data line by said first system within a time window, said time window terminates before a minimum possible duration of said first time duration; (e) and when said current operating mode is said write mode, (e1) driving said data line toward a data voltage level dependent upon said at least one data bit of said serial block transfers of data said data voltage level approximately equal to said first voltage level or said second voltage level; (e2) waiting for a second time duration, said second time duration having a second length, said second length dependent upon said at least one data bit of said serial block transfers of data and then testing the at least one voltage state of said data line to ascertain the at least one data bit of said serial block transfers of data written; and (e3) in said first system, holding said data line to said data voltage level over said time window which begins before an earliest possible expiration, for said at least one second system of said second time duration, and which ends after a latest possible expiration, of said second time duration.
Claim 2
Independent Claim
471 words
A method for data communication by serial block transfers of data on a data line between a first system and at least one second system, said serial block transfers of data having at least one data bit and said data line having at least one voltage state, comprising the steps of: (a) defining a current operating mode to be either a write mode or a read mode, so that said at least one data bit of said serial block transfers of data is transferred from said first system to said at least one second system when said current operating mode is said write mode and said at least one data bit of said serial block transfers of data is transferred from said at least one second system to said first system when said current operating mode is said read mode; (b) driving said data line toward a first voltage level by said first system and thereafter driving said data line to make a transition of said data line toward a second voltage; (c) detecting said transition of said data line toward said second voltage level by said at least one second system; (d) and when said current operating mode is said read mode, (d1) driving said data line toward said second voltage level by said at least one second system and holding said data line at said second voltage level for a first time duration, said first time duration having a first length, said first length dependent upon said at least one data bit of said serial block transfers of data and releasing said data line after said first time duration, and (d2) testing the at least one voltage state of said data line by said first system within a time window, said time window terminates before a minimum possible duration of said first time duration; (e) and when said current operating mode is said write mode, (e1) driving said data line toward a data voltage level dependent upon said at least one data bit of said serial block transfers of data said data voltage level approximately equal to said first voltage level or said second voltage level; (e2) waiting for a second time duration, said second time duration having a second length, said second length dependent upon said at least one data bit of said serial block transfers of data and then testing the at least one voltage state of said data line to ascertain the at least one data bit of said serial block transfers of data written; and (e3) in said first system, holding said data line to said data voltage level over said time window which begins before an earliest possible expiration, for said at least one second system of said second time duration, and which ends after a latest possible expiration, of said second time duration.
Claim 3
Dependent Claim
88 words
The method of claim 1, wherein said serial block transfers of data have a first block transfer, each block of said first block transfer of data having a beginning, and further comprising the additional step of, at the beginning of the first block transfer of data between said first system and said at least one second system, performing an address-pointer-reset operation, by sending from said first system to said at least one second system, a data sequence which could not possibly occur during said read or write modes.
Claim 4
Dependent Claim
79 words
The method of claim 1, wherein said block transfers of data has a beginning, and further comprising the additional step of, at the beginning of each block transfer of data of said block transfers of data between said first system and said at least one second system, transmitting overhead bits from said first system to said at least one second system, to selectably place said at least one second system in said read mode or in said write mode.
Claim 5
Dependent Claim
18 words
The method of claim 1, wherein said first time duration is substantially equal to said second time duration.
Claim 6
Dependent Claim
33 words
The method of claim 1, wherein said first voltage corresponds to a logical high and is approximately 5 volts and said second voltage corresponds to a logical low and is approximately 0 volts.
Claim 7
Dependent Claim
20 words
The method of claim 1, wherein said first time duration and said second time duration is at least one microsecond.
Claim 8
Dependent Claim
17 words
The method of claim 1, wherein said time window is at least 30 microseconds from said transition.
Claim 9
Dependent Claim
14 words
The method of claim 1, wherein said second system is a button-shaped electronic token.
Claim 10
Dependent Claim
20 words
The method of claim 1, wherein said first system and said at least one second system is an integrated circuit.
Claim 11
Dependent Claim
36 words
The method of claim 1, wherein said testing that occurs in both read and write modes is performed for each data bit(s) of said data, so that data bit(s) are read or written bit by bit.
Claim 12
Dependent Claim
72 words
The method of claim 1, wherein after said driving said data line toward a first voltage level by said first system and before driving said data line to make a transition of said data line toward a second voltage, comprising the following step of holding said data line for a first time period that is long enough to ensure that an edge detector in said second system will have sufficient set-up time.
Claim 13
Dependent Claim
20 words
The method of claim 1, wherein said second voltage level is approximately ground and corresponds to a logic low level.
Claim 14
Dependent Claim
20 words
The method of claim 1, wherein said transition provides a coordinating time from which said second system coordinates internal operations.
Claim 15
Dependent Claim
15 words
The method of claim 1, wherein said first time length is at least one microsecond.
Claim 16
Dependent Claim
15 words
The method of claim 1, wherein said second time length is at least one microsecond.
Claim 17
Dependent Claim
16 words
The method of claim 1, further comprising the following steps: (f) repeating steps (a) through (e).
Claim 18
Dependent Claim
17 words
The method of claim 1, wherein said time window is at least 30 microseconds from said transition.
Claim 19
Dependent Claim
25 words
The method of claim 1, wherein said data bit is selected from the group consisting of a logical one value and a logical zero value.
Claim 20
Dependent Claim
34 words
The method of claim 1, wherein said first length of said first time duration and said second length of said second time duration when combined together do not exceed 60 microseconds from said transition.
Claim 21
Dependent Claim
46 words
The method of claim 1, wherein said first length of said first duration and said second length of said second duration when combined together create a fourth time duration having a fourth length which is approximately four times said second length of said second time duration.
Claim 22
Dependent Claim
15 words
The method of claim 1, wherein said first system performs steps (a), (b), and (c).
Claim 23
Dependent Claim
15 words
The method of claim 1, wherein said at least one second system performs step (d).
Claim 24
Dependent Claim
12 words
The method of claim 1, wherein said transition is a falling edge.
Claim 25
Dependent Claim
30 words
The method of claim 1, wherein said transition has a corresponding transition time and a corresponding transition rate, said corresponding transition time and said corresponding transition rate vary with temperature.
Claim 26
Dependent Claim
21 words
The method of claim 1, wherein said first voltage level is approximately five volts and corresponds to a logic high level.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-13 | 1998-09-12 | 1999-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-13 | 2002-09-12 | 2003-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-13 | 2006-09-12 | 2007-03-14 | $7700.00 | Window Closed / Lapsed |