Write-once-read-once batteryless authentication token

Claim 2

A write-once-read-once token security system for allowing limited access to a secure system comprising: a token comprising an array of fuse links; means for writing data into said array by blowing selected ones of said fuse links; and means for reading data out of said array, said means for reading data in addition blowing fuse links in said array not already blown by said means for writing data.

Claim 3

The token security system recited in claim 1 wherein said array of fuse links is composed of first and second arrays of fuse links, said token further comprising multiplexer means connected to said first and second arrays and responsive to said means for reading data for selectively reading data from one or the other of said first and second arrays.

Claim 4

The token security system recited in claim 1 wherein said means for writing comprises: data latch means for temporarily storing data to be read into said array; demultiplexer means for addressing individual fuse links in said array; and counter means connected to said demultiplexer means for cycling through addresses for each of said fuse links, said demultiplexer means connecting said data latch means to an addressed fuse link.

Claim 5

The token security system recited in claim 3 wherein said counter means counts 2n addresses, where n is the number of fuse links in said array, said token security system further comprising inhibiting means responsive to an nth address output of said counter means to inhibit the connection of said data latch means to an addressed fuse link, said means for reading further clocking said counter to read data out of said array.

Claim 6

The token security system recited in claim 1 wherein said array of fuse links is composed of first and second arrays of fuse links, said token further comprising multiplexer means connected to said first and second arrays and responsive to said means for reading data for selectively reading data from one or the other of said first and second arrays and wherein said means for writing comprises: first and second data latch means for temporarily storing data to be respectively read into said first and second arrays; first and second demultiplexer means for respectively addressing individual fuse links in said first and second arrays; and counter means connected to said first and second demultiplexer means for cycling through addresses for each of said fuse links, said first and second demultiplexer means respectively connecting said first and second data latch means to an addressed fuse link in said first and second arrays.

Claim 7

The token security system recited in claim 5 wherein said counter means counts 2n addresses, where n is the number of fuse links in each of said first and second arrays, said token security system further comprising inhibiting means responsive to an nth address output of said counter means to inhibit the connection of said first and second data latch means to an addressed fuse link, said means for reading further clocking said counter means to read data out of said first and second arrays.

Claim 8

The token security system recited in claim 6 further comprising third and fourth latch means respectively connected between said first and second arrays and said multiplexer means for temporarily storing data read out of said first and second arrays.

Claim 9

A write-once-read-once token for authorizing access to a secure system comprising: first and second arrays of fuse links; multiplexer means connected to said first and second arrays for selectively reading data from one or the other of said first and second arrays: first and second data latch means for temporarily storing data to be respectively read into said first and second arrays; respectively addressing individual fuse links in said first and second arrays; and counter means connected to said first and second demultiplexer means for cycling through addresses for each of said fuse links, said first and second demultiplexer means respectively connecting said first and second data latch means to an addressed fuse link in said first and second arrays.

Claim 10

A write-once-read-once token for authorizing access to a secure system comprising: first and second arrays of fuse links; multiplexer means connected to said first and second arrays for selectively reading data from one or the other of said first and second arrays: first and second data latch means for temporarily storing data to be respectively read into said first and second arrays; respectively addressing individual fuse links in said first and second arrays; and counter means connected to said first and second demultiplexer means for cycling through addresses for each of said fuse links, said first and second demultiplexer means respectively connecting said first and second data latch means to an addressed fuse link in said first and second arrays.

Claim 11

The token recited in claim 8 wherein said counter means counts 2n addresses, where n is the number of fuse links in each of said first and second arrays, said token security system further comprising inhibiting means responsive to an nth address output of said counter means to inhibit the connection of said first and second data latch means to an addressed fuse link, said counter means being further clocked to read data out of said first and second arrays.

Claim 12

The token security system recited in claim 9 further comprising third and fourth latch means respectively connected between said first and second arrays and said multiplexer means for temporarily storing data read out of said first and second arrays.

Claim 13

A physically secure forgery-resistant authorization system comprising: an output device; a token including storage means including at least first and second distinct storage elements for electronically storing information and for coupling signals representative of a selected portion of said stored information to said output device, said storage means requiring no sustaining power when not in use; a connector for coupling said token to said output device, said connector including a query input terminal, token clock input terminal, and an output response terminal; means for connecting said query input terminal to said token; said token including selection means responsive to signals on said query input terminal for selecting and coupling to said connector signals from either said first or second distinct storage elements, said token further including means, simultaneous with said coupling, for destroying unselected information, whereby after selected information is output neither said first nor said second distinct storage elements retain said unselected stored information.

Claim 14

A physically secure forgery-resistant authorization system comprising: an output device; a token including storage means including at least first and second distinct storage elements for electronically storing information and for coupling signals representative of a selected portion of said stored information to said output device, said storage means requiring no sustaining power when not in use; a connector for coupling said token to said output device, said connector including a query input terminal, token clock input terminal, and an output response terminal; means for connecting said query input terminal to said token; said token including selection means responsive to signals on said query input terminal for selecting and coupling to said connector signals from either said first or second distinct storage elements, said token further including means, simultaneous with said coupling, for destroying unselected information, whereby after selected information is output neither said first nor said second distinct storage elements retain said unselected stored information.

Claim 15

A physically secure authorization device as recited in claim 11 wherein said first and second distinct storage elements comprise first and second memory arrays and means connecting said query terminal and said clock terminal to said memory arrays for selecting elements of said memory arrays, whereby after a number of clock pulses have been received equal in number to twice the capacity of said first and second memory arrays, both said first and second memory arrays will no longer retain said stored information.

Claim 16

A physically secure authorization device as recited in claim 12 wherein said selection means comprises addressing means responsive to clock pulses on said clock terminal for addressing both of said first and second memory arrays.

Claim 17

A physically secure authorization device as recited in claim 13 wherein said selection means also includes multiplexer means responsive to a query signal on said query input terminal for selecting an addressed output from one of said first or second memory arrays, said selected output being supplied on said output response terminal.

Claim 18

A physically secure authorization device as recited in claim 12 in which said selection means comprises: counter means responsive to clock pulses on said clock terminal for generating addresses; first and second demultiplexer means responsive to said addresses for reading out data bits from said first and second memory arrays, respectively; and multiplexer means responsive to a query signal on said query input terminal for selecting an addressed output from one of said first or second memory arrays, said selected output being supplied on said output response terminal.

Claim 19

A physically secure authorization device as recited in claim 11 in which said storage means and said output device are implemented as an integrated circuit.

Claim 20

A physically secure authorization device as recited in claim 11 in which said storage means and said output device are enclosed within a tamper resistant package.

Claim 21

A physically secure authorization device as recited in claim 11 in which said storage means comprises a memory array wherein said first and second distinct storage elements comprise different addressable storage locations, and wherein said selection means includes counter means with an input coupled to said token clock input of said connector for addressing said memory array.

Claim 22

A physically secure authorization device as recited in claim 18 in which said connector further includes at least a data input terminal coupled to at least one input of said distinct storage elements.

Claim 23

A physically secure authorization device as recited in claim 18 in which said memory arrays store bits in the physical state of an electronic component.

Claim 24

A physically secure authorization device as recited in claim 20 where said electronic component is a fusible link device.

Claim 25

A physically secure authorization device as recited in claim 11 in which said connector further includes at least a data input terminal coupled to at least one input of said distinct storage elements.

Claim 26

A physically secure forgery-resistant authorization device comprising: storage means for retaining stored information; a connector with an output terminal and a query input; first means responsive to query information represented by said query input for selecting and coupling to said output terminal signals representative of a selected portion of said stored information only after destroying both the selected permanently stored information and an equal quantity of unselected stored information, whereby before said selected information is output via said connector, said device no longer retains said equal quantity of said unselected stored information.

Claim 27

A physically secure forgery-resistant authorization device comprising: storage means for retaining stored information; a connector with an output terminal and a query input; first means responsive to query information represented by said query input for selecting and coupling to said output terminal signals representative of a selected portion of said stored information only after destroying both the selected permanently stored information and an equal quantity of unselected stored information, whereby before said selected information is output via said connector, said device no longer retains said equal quantity of said unselected stored information.

Claim 28

A physically secure authorization device as recited in claim 23 wherein said first means further includes means for destroying said selected stored information so that before said selected stored information is output from said output terminal, said device no longer retains in a permanent form either said selected or said unselected stored information.

Claim 29

A physically secure authorization device as recited in claim 23 wherein said connector further includes a clock terminal and said storage means comprise memory arrays, said first means comprises: address means connected to said clock terminal for generating addresses of data stored in said memory arrays; and selector means for selecting addressed data in said memory arrays for coupling to said output terminal.

Claim 30

A physically secure authorization device as recited in claim 25 in which said selector means includes latch means for temporarily storing said selected addressed data.