US5398245A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Packet processing method and apparatus
Assignee: Avaya Holdings Ltd
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Filing: 1991-10-04
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Granted: 1995-03-14
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Expires: 2011-10-04
Abstract
Abstract A method and apparatus for processing a data packet, for delivery to a designated location, store selective portions of the packet header in a high speed cache memory to increase processing speed and hence throughput for a packet delivery system. The apparatus and method receive the packets from a data channel source and store portions of the header in cache, and at least the remainder of each data packet is stored in a slower speed memory. A CPU accesses the stored header portion of each packet in cache for necessary protocol and destination information processing of the data packet. The header portions are then overwritten with new data and combined with the remainder of the data packet stored in slower speed memory for transmission to the next packet destination. Preferably, the address at which the remainder portions are stored in slower speed memory determine the cache addresses at which the header portion is stored in high speed cache memory.
Inventors
- 👤 Edward S. Harriman, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:08
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/90; H04L49/9047; G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F7/00; G06F7/38; H04L49/901; H04L49/9042; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/3808; G06F2207/3832; H04L67/00; H04L67/50; H04L67/56; H04L67/568; H04L69/00; H04L69/22
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
149 words
A method for processing a data packet for delivery to a designated destination, said data packet having a selected protocol, said data packet including a header and a remainder portion, wherein said header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising the steps of receiving successive data packets from a data source channel, storing at least a portion of said header of each data packet in a high speed data cache memory, storing at least said remainder portion of said each data packet in a slower speed memory, accessing each header of said each data packet in said high speed data cache memory for protocol and destination processing of said each data packet, and forwarding a new data packet to a next data packet destination based on the designated protocol and destination processing of said each data packet.
Claim 2
Independent Claim
149 words
A method for processing a data packet for delivery to a designated destination, said data packet having a selected protocol, said data packet including a header and a remainder portion, wherein said header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising the steps of receiving successive data packets from a data source channel, storing at least a portion of said header of each data packet in a high speed data cache memory, storing at least said remainder portion of said each data packet in a slower speed memory, accessing each header of said each data packet in said high speed data cache memory for protocol and destination processing of said each data packet, and forwarding a new data packet to a next data packet destination based on the designated protocol and destination processing of said each data packet.
Claim 3
Dependent Claim
38 words
The method of claim 1 further comprising the step of storing said header of said each data packet at an address identifying the location in said slower speed memory of said remainder portion of said each data packet.
Claim 4
Dependent Claim
46 words
The method of claim 1 further comprising the step of identifying, from an address in said slower speed memory at which said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which said header is stored.
Claim 5
Dependent Claim
64 words
The method of claim 1 further comprising the steps of providing plural port access to said high speed data cache memory from at least an input/output data bus and a CPU based processor, reading said stored header directly from said high speed data cache memory by said processor, and writing to said high speed data cache memory from said processor for modifying said header.
Claim 6
Dependent Claim
23 words
The method of claim 1 further comprising the step of storing non-adjacent portions of said header in said high speed data cache memory.
Claim 7
Dependent Claim
40 words
The method of claim 1 further comprising the step of selecting portions of said header for storage in said high speed data cache memory depending upon the address in said slower speed memory into which said remainder portion is stored.
Claim 8
Independent Claim
281 words
A method for processing a data packet for delivery to a designated destination, said data packet having a selected protocol and including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising the steps of receiving successive data packets from a data source channel, storing non-contiguous portions of the header of each data packet in a high speed data cache memory, storing at least said remainder portion of said each data packet in a slower speed memory, selecting portions of said header of said each data packet for storage in said high speed data cache memory depending upon the address in the slower speed memory into which an associated remainder portion is stored, identifying, from an address in the slower speed memory at which said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which the selected portion corresponding to said associated remainder portion is stored, accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of said each data packet, said accessing step comprising providing plural port access to said high speed data cache memory from at least an input/output data bus and a CPU based processor, reading said stored header directly from said high speed data cache memory by said processor, and writing to said high speed data cache memory from said processor for modifying said header, and forwarding a new data packet to a next data packet destination based on the designated protocol and destination processing of the data packet.
Claim 9
Independent Claim
281 words
A method for processing a data packet for delivery to a designated destination, said data packet having a selected protocol and including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising the steps of receiving successive data packets from a data source channel, storing non-contiguous portions of the header of each data packet in a high speed data cache memory, storing at least said remainder portion of said each data packet in a slower speed memory, selecting portions of said header of said each data packet for storage in said high speed data cache memory depending upon the address in the slower speed memory into which an associated remainder portion is stored, identifying, from an address in the slower speed memory at which said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which the selected portion corresponding to said associated remainder portion is stored, accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of said each data packet, said accessing step comprising providing plural port access to said high speed data cache memory from at least an input/output data bus and a CPU based processor, reading said stored header directly from said high speed data cache memory by said processor, and writing to said high speed data cache memory from said processor for modifying said header, and forwarding a new data packet to a next data packet destination based on the designated protocol and destination processing of the data packet.
Claim 10
Independent Claim
164 words
An apparatus for processing a data packet for delivery to a designated destination, said data packet having a selected protocol, said data packet including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising means for receiving successive data packets from a data source channel, a high speed data cache memory, a slower speed memory, means for storing at least a portion of said header of each data packet in said high speed data cache memory, means for storing at least said remainder portion of said each data packet in said slower speed memory, means for accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of the data packet, and means for forwarding a new data packet to a next data packet destination based on the designated protocol and destination processing of said data packet.
Claim 11
Independent Claim
164 words
An apparatus for processing a data packet for delivery to a designated destination, said data packet having a selected protocol, said data packet including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising means for receiving successive data packets from a data source channel, a high speed data cache memory, a slower speed memory, means for storing at least a portion of said header of each data packet in said high speed data cache memory, means for storing at least said remainder portion of said each data packet in said slower speed memory, means for accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of the data packet, and means for forwarding a new data packet to a next data packet destination based on the designated protocol and destination processing of said data packet.
Claim 12
Dependent Claim
38 words
The apparatus of claim 8 further comprising means for storing each said header portion of a data packet at an address identifying the location in said slower speed memory of the remainder portion of the associated data packet.
Claim 13
Dependent Claim
46 words
The apparatus of claim 8 further comprising means for identifying from an address in said slower speed memory at which each said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which said header is stored.
Claim 14
Dependent Claim
64 words
The apparatus of claim 8 further comprising means for providing plural port access to said high speed data cache memory from input/output data bus and a CPU based processor, means for reading said stored header directly from said high speed data cache memory by said processor, and means for writing to said high speed data cache memory from said processor for modifying said header.
Claim 15
Dependent Claim
22 words
The apparatus of claim 8 further comprising means for storing non-adjacent portions of said header in said high speed data cache memory.
Claim 16
Dependent Claim
37 words
The apparatus of claim 8 further comprising means for selecting portions of said header for storage in said high speed data cache memory depending upon the address in slow memory into which said remainder portion is stored.
Claim 17
Independent Claim
290 words
An apparatus for processing a data packet for delivery to a designated destination, said data packet having a selected protocol, said data packet including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising means for receiving successive data packets from a data source channel, a multi-port high speed data cache memory, means for connecting said high speed data cache memory to an input/output data bus and a CPU based processor, a slower speed memory, means for storing non-contiguous portions of said header of each data packet in said high speed data cache memory, means for storing at least said remainder portion of said each data packet in said slower speed memory, means for selecting portions of said header for storage in said high speed data cache memory depending upon the address in said slower speed memory into which said remainder portion is stored, means for accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of said data packet, said accessing means having means for identifying from an address in said slower speed memory at which said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which said header is stored, means for reading said stored header directly from said high speed data cache memory by said processor, and means for writing to said high speed data cache memory from said processor for modifying said header, and means for forwarding a new data packet to a next data packet destination based on the protocol and destination processing of said data packet.
Claim 18
Independent Claim
290 words
An apparatus for processing a data packet for delivery to a designated destination, said data packet having a selected protocol, said data packet including a header and a remainder portion, wherein the header of said data packet includes at least one of destination identification data, protocol data, and source identification data, comprising means for receiving successive data packets from a data source channel, a multi-port high speed data cache memory, means for connecting said high speed data cache memory to an input/output data bus and a CPU based processor, a slower speed memory, means for storing non-contiguous portions of said header of each data packet in said high speed data cache memory, means for storing at least said remainder portion of said each data packet in said slower speed memory, means for selecting portions of said header for storage in said high speed data cache memory depending upon the address in said slower speed memory into which said remainder portion is stored, means for accessing said header of said each data packet in said high speed data cache memory for protocol and destination processing of said data packet, said accessing means having means for identifying from an address in said slower speed memory at which said remainder portion of said each data packet is stored, an address in said high speed data cache memory at which said header is stored, means for reading said stored header directly from said high speed data cache memory by said processor, and means for writing to said high speed data cache memory from said processor for modifying said header, and means for forwarding a new data packet to a next data packet destination based on the protocol and destination processing of said data packet.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-13 | 1998-09-12 | 1999-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-13 | 2002-09-12 | 2003-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-13 | 2006-09-12 | 2007-03-14 | $7700.00 | Window Closed / Lapsed |