US5394541A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable memory timing method and apparatus for programmably generating generic and then type specific memory timing signals
Assignee: Xerox Corp
•
Filing: 1991-12-20
•
Granted: 1995-02-28
•
Expires: 2011-12-20
Abstract
Abstract The present invention operates within a data processing system with multiple DRAM memory modules, providing programmable memory timing through the use of a RAM within the memory controller unit of the data processing system. This RAM, termed the MCRAM, is used to store the timing information for memory operations. In particular, the MCRAM stores for each of the memory operations, Read, Write, and Refresh, the relevant information for RAS, CAS, LD, and AD timing signals. The presently preferred embodiment of the invention contemplates a particular programming process wherein the MCRAM is initially loaded with generic timing information which is acceptable to all possible DRAM memory modules. Following this loading operation, the processor obtains the ID number of the DRAMs within a particular memory module. This ID number is used in a look-up table to obtain the vendor-specific optimal timing for DRAMs corresponding to this ID number. The processor then writes this optimal timing information into the MCRAM. Thereafter, all memory operations to this particular memory module utilize this optimal timing information.
Inventors
- 👤 Gilman Chesley
- 👤 Jean A. Gastinel
- 👤 Fred Cerauskis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 21:34
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G11; G11C; G11C8/00; G11C8/12; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; G11C7/00; G11C7/22
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
272 words
A method of programming memory timing of a data processing system, said data processing system including a processor, a memory for storing and retrieving data in accordance with timing signals, and a memory controller for providing said timing signals to said memory, said memory controller including a programmable memory timing generator for generating said timing signals from timing data, said timing data comprising generic timing data representing generic timing signals suitable for use with a plurality of types of predetermined memory types and a plurality of memory type specific timing data, each said memory type specific timing data representing memory type specific timing signals suitable for use with a corresponding memory type of said plurality of types of predetermined memories, said data processing system further including a look-up table, said look-up table being accessible to said processor and storing said timing data, said method comprising the steps of: loading said generic timing data into said programmable memory timing generator; generating generic timing signals from said generic timing data and providing generic timing signals to said memory; using said generic timing signals to access said memory to identify a specific type of memory of said memories of said processing system; reading from said look-up table corresponding type specific timing data for said identified specific type of memory; writing said corresponding type specific timing data for said identified specific type of memory into said programmable memory timing generator and thereby programming said identified specific timing data into said programmable memory timing generator; and generating type specific timing signals from said identified specific timing data and providing said type specific timing signals to said memory.
Claim 2
Independent Claim
272 words
A method of programming memory timing of a data processing system, said data processing system including a processor, a memory for storing and retrieving data in accordance with timing signals, and a memory controller for providing said timing signals to said memory, said memory controller including a programmable memory timing generator for generating said timing signals from timing data, said timing data comprising generic timing data representing generic timing signals suitable for use with a plurality of types of predetermined memory types and a plurality of memory type specific timing data, each said memory type specific timing data representing memory type specific timing signals suitable for use with a corresponding memory type of said plurality of types of predetermined memories, said data processing system further including a look-up table, said look-up table being accessible to said processor and storing said timing data, said method comprising the steps of: loading said generic timing data into said programmable memory timing generator; generating generic timing signals from said generic timing data and providing generic timing signals to said memory; using said generic timing signals to access said memory to identify a specific type of memory of said memories of said processing system; reading from said look-up table corresponding type specific timing data for said identified specific type of memory; writing said corresponding type specific timing data for said identified specific type of memory into said programmable memory timing generator and thereby programming said identified specific timing data into said programmable memory timing generator; and generating type specific timing signals from said identified specific timing data and providing said type specific timing signals to said memory.
Claim 3
Dependent Claim
27 words
The method of programming the memory timing of a data processing system as provided in claim 1, wherein said look-up table is disposed on a magnetic disc.
Claim 4
Dependent Claim
29 words
The method of programming the memory timing of a data processing system as provided in claim 1, wherein said look-up table is disposed on a read only memory (ROM).
Claim 5
Dependent Claim
31 words
The method of programming the memory timing of a data processing system as provided in claim 1, wherein said programmable memory timing generator comprises at least one random access memory (RAM).
Claim 6
Dependent Claim
37 words
The method of programming the memory timing of a data processing system as provided in claim 1, wherein said specific type of memory is identified by an ID code provided by said memory to said memory controller.
Claim 7
Dependent Claim
24 words
The method of programming the memory timing of a data processing system as provided in claim 5, wherein said ID code is a number.
Claim 8
Dependent Claim
29 words
The method of programming the memory timing of a data processing system as provided in claim 1, wherein said memory comprises at least one dynamic random access memory (DRAM).
Claim 9
Dependent Claim
36 words
The method of programming the memory timing of a data processing system as provided in claim 7, wherein said type of DRAM is identified by an ID code provided by said DRAM to said memory controller.
Claim 10
Dependent Claim
24 words
The method of programming the memory timing of a data processing system as provided in claim 8, wherein said ID code is a number.
Claim 11
Dependent Claim
326 words
In a data processing system including a processor, a memory for storing and retrieving data in accordance with timing signals, and a memory controller for providing said timing signals to said memory, said memory controller including a programmable memory timing generator for generating said timing signals from timing data, said data processing system further including a look-up table, said look-up table being accessible to said processor and storing said timing data, said timing data comprising generic timing data representing generic timing signals suitable for use with a plurality of types of predetermined memory types and a plurality of memory type specific timing data, each said memory type specific timing data representing memory type specific timing signals suitable for use with a corresponding memory type of said plurality of types of predetermined memory types, an apparatus for programming the memory timing of said data processing system, said apparatus comprising: generic timing loader coupled to said programmable memory timing generator, said generic timing loader for loading into said programmable memory timing generator said generic timing data; type identifier coupled to said memory, said type identifier for identifying the specific type of memory of said data processing system using said generic timing signals to access said memory; reader coupled to said type identifier and said look-up table, said reader for reading from said look-up table the type specific timing data corresponding to said identified memory; writer coupled to said reader and to said programmable memory timing generator, said writer for writing said type specific timing data corresponding to said identified memory into said programmable memory timing generator after said identified memory has been identified and thereby programming said identified type specific timing data into said programmable memory timing generator so that, once programmed with said identified type specific timing data, said programmable timing generator will generate identified type specific timing signals from said identified type specific timing data and provide said identified type specific timing signals to said memory.
Claim 12
Dependent Claim
326 words
In a data processing system including a processor, a memory for storing and retrieving data in accordance with timing signals, and a memory controller for providing said timing signals to said memory, said memory controller including a programmable memory timing generator for generating said timing signals from timing data, said data processing system further including a look-up table, said look-up table being accessible to said processor and storing said timing data, said timing data comprising generic timing data representing generic timing signals suitable for use with a plurality of types of predetermined memory types and a plurality of memory type specific timing data, each said memory type specific timing data representing memory type specific timing signals suitable for use with a corresponding memory type of said plurality of types of predetermined memory types, an apparatus for programming the memory timing of said data processing system, said apparatus comprising: generic timing loader coupled to said programmable memory timing generator, said generic timing loader for loading into said programmable memory timing generator said generic timing data; type identifier coupled to said memory, said type identifier for identifying the specific type of memory of said data processing system using said generic timing signals to access said memory; reader coupled to said type identifier and said look-up table, said reader for reading from said look-up table the type specific timing data corresponding to said identified memory; writer coupled to said reader and to said programmable memory timing generator, said writer for writing said type specific timing data corresponding to said identified memory into said programmable memory timing generator after said identified memory has been identified and thereby programming said identified type specific timing data into said programmable memory timing generator so that, once programmed with said identified type specific timing data, said programmable timing generator will generate identified type specific timing signals from said identified type specific timing data and provide said identified type specific timing signals to said memory.
Claim 13
Dependent Claim
27 words
The method of programming the memory timing of a data processing system as provided in claim 10, wherein said look-up table is disposed on a magnetic disc.
Claim 14
Dependent Claim
29 words
The method of programming the memory timing of a data processing system as provided in claim 10, wherein said look-up table is disposed on a read only memory (ROM).
Claim 15
Dependent Claim
31 words
The method of programming the memory timing of a data processing system as provided in claim 10, wherein said programmable memory timing generator comprises at least one random access memory (RAM).
Claim 16
Dependent Claim
37 words
The method of programming the memory timing of a data processing system as provided in claim 10, wherein said specific type of memory is identified by an ID code provided by said memory to said memory controller.
Claim 17
Dependent Claim
24 words
The method of programming the memory timing of a data processing system as provided in claim 14, wherein said ID code is a number.
Claim 18
Dependent Claim
29 words
The method of programming the memory timing of a data processing system as provided in claim 10, wherein said memory comprises at least one dynamic random access memory (DRAM).
Claim 19
Dependent Claim
36 words
The method of programming the memory timing of a data processing system as provided in claim 16, wherein said type of DRAM is identified by an ID code provided by said DRAM to said memory controller.
Claim 20
Dependent Claim
24 words
The method of programming the memory timing of a data processing system as provided in claim 17, wherein said ID code is a number.
Claim 21
Independent Claim
243 words
An apparatus for programmably providing N timing signals for a memory module, where N is a positive integer, each said timing signal having a period of M clock cycles, where M is a positive integer having a value at least greater than one, said apparatus comprising: a random access memory (RAM), said RAM comprising a matrix of M lines and N columns, each line of said M lines having N memory cells and corresponding to a different one of said M clock cycles, each said memory cell of said line corresponding to a different one of said N timing signals and holding one bit of information regarding whether or not said corresponding timing signal is to be asserted during said corresponding clock cycle; a loader coupled to said RAM, said loader for loading said matrix with said information bits; a RAM control counter coupled to said RAM; and memory control logic coupled to said RAM, said RAM control counter controlling said RAM and causing said RAM to repeatedly cycle through said M lines sequentially selecting one of said M lines, said RAM providing said N information bits of said selected line to said memory control logic, said memory control logic mapping each said information bit of said selected line to one said timing signal of said N timing signals and asserting or not asserting at least one of said timing signals based on the value of said information bits of said selected line.
Claim 22
Independent Claim
243 words
An apparatus for programmably providing N timing signals for a memory module, where N is a positive integer, each said timing signal having a period of M clock cycles, where M is a positive integer having a value at least greater than one, said apparatus comprising: a random access memory (RAM), said RAM comprising a matrix of M lines and N columns, each line of said M lines having N memory cells and corresponding to a different one of said M clock cycles, each said memory cell of said line corresponding to a different one of said N timing signals and holding one bit of information regarding whether or not said corresponding timing signal is to be asserted during said corresponding clock cycle; a loader coupled to said RAM, said loader for loading said matrix with said information bits; a RAM control counter coupled to said RAM; and memory control logic coupled to said RAM, said RAM control counter controlling said RAM and causing said RAM to repeatedly cycle through said M lines sequentially selecting one of said M lines, said RAM providing said N information bits of said selected line to said memory control logic, said memory control logic mapping each said information bit of said selected line to one said timing signal of said N timing signals and asserting or not asserting at least one of said timing signals based on the value of said information bits of said selected line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-27 | 1998-08-29 | 1999-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-27 | 2002-08-29 | 2003-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-27 | 2006-08-29 | 2007-02-28 | $7700.00 | Window Closed / Lapsed |