Patent US5393679A successfully refreshed from Google Patents.
US5393679A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Use of double charge implant to improve retrograde process PMOS punch through voltage
Assignee: United Microelectronics Corp
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Filing: 1994-04-05
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Granted: 1995-02-28
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Expires: 2014-04-05
Abstract
Abstract A semiconductor CMOS device on a silicon substrate doped with an N- dopant is manufactured by a process of forming a mask upon the substrate, forming field oxide structures upon the substrate through the mask, removing the mask, forming a sacrificial layer on the surface of the substrate between the field oxide structures, forming a P-well mask on the substrate for the NMOS portion of the device, implanting dopant ions to form an NMOS retrograde P-well through the P-well mask, performing an NMOS V T first implant of ions through the P-well mask into selected regions of the the substrate, performing a second V T implant of ions into the substrate, performing a PMOS punchthrough voltage implant of ions into the substrate, forming doped polysilicon gate structures, and forming doped source/drain regions.
Inventors
- 👤 Sheng-Hsing Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:48
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
107 words
A method of manufacture of a semiconductor CMOS device on a silicon substrate doped with an N- dopant comprising: a) forming a P-well mask on said substrate for the NMOS portion of said device, b) implanting dopant ions to form an NMOS retrograde P-well through said P-well mask, c) performing an NMOS first V T implant of ions into said substrate, d) removing said P-well mask and performing a second V T implant of ions into said substrate, e) performing a PMOS punchthrough voltage implant of ions into said substrate, f) forming of doped polysilicon gate structures above said substrate, and g) forming of doped source/drain regions.
Claim 2
Independent Claim
107 words
A method of manufacture of a semiconductor CMOS device on a silicon substrate doped with an N- dopant comprising: a) forming a P-well mask on said substrate for the NMOS portion of said device, b) implanting dopant ions to form an NMOS retrograde P-well through said P-well mask, c) performing an NMOS first V T implant of ions into said substrate, d) removing said P-well mask and performing a second V T implant of ions into said substrate, e) performing a PMOS punchthrough voltage implant of ions into said substrate, f) forming of doped polysilicon gate structures above said substrate, and g) forming of doped source/drain regions.
Claim 3
Dependent Claim
48 words
A method in accordance with claim 1 wherein said first V T implant of ions is performed with a dosage of from about 7×10 11 cm -2 to about 9×10 11 cm -2 , with an energy within a range from about 40 keV to about 80 keV.
Claim 4
Dependent Claim
48 words
A method in accordance with claim 2 wherein said second V T implant of ions is performed with a dosage of from about 1×10 12 cm -2 to about 3×10 12 cm -2 , with an energy within a range from about 40 keV to about 80 keV.
Claim 5
Dependent Claim
45 words
A method in accordance with claim 3 wherein said PMOS punchthrough voltage implant of ions comprises a double charge with a dose from about 2.4×10 12 to about 4×10 12 , with an energy within a range from about 380 keV to about 400 keV.
Claim 6
Dependent Claim
27 words
A method in accordance with claim 4 wherein said retrograde implant dopant comprises BF 2 + ions and said punchthrough implant dopant comprises 31 P +2 ions.
Claim 7
Independent Claim
142 words
A method of manufacture of a semiconductor CMOS device on a silicon substrate doped with an N- dopant comprising: a) forming a mask upon said substrate, b) forming field oxide structures upon said substrate through said mask, removing said mask, c) forming a sacrificial layer on the surface of said substrate between said field oxide structures, d) forming a P-well mask on said substrate for the NMOS portion of said device, e) implanting dopant ions to form an NMOS retrograde P-well through said P-well mask, f) performing an NMOS V T first implant of ions through said P-well mask into selected regions of said said substrate, g) performing a second V T implant of ions into said substrate, h) performing a PMOS punchthrough voltage implant of ions into said substrate, i) forming doped polysilicon gate structures, and j) forming doped source/drain regions.
Claim 8
Independent Claim
142 words
A method of manufacture of a semiconductor CMOS device on a silicon substrate doped with an N- dopant comprising: a) forming a mask upon said substrate, b) forming field oxide structures upon said substrate through said mask, removing said mask, c) forming a sacrificial layer on the surface of said substrate between said field oxide structures, d) forming a P-well mask on said substrate for the NMOS portion of said device, e) implanting dopant ions to form an NMOS retrograde P-well through said P-well mask, f) performing an NMOS V T first implant of ions through said P-well mask into selected regions of said said substrate, g) performing a second V T implant of ions into said substrate, h) performing a PMOS punchthrough voltage implant of ions into said substrate, i) forming doped polysilicon gate structures, and j) forming doped source/drain regions.
Claim 9
Dependent Claim
48 words
A method in accordance with claim 6 wherein said first V T implant of ions is performed with a dosage of from about 7×10 11 cm -2 to about 9×10 11 cm -2 , with an energy within a range from about 40 keV to about 80 keV.
Claim 10
Dependent Claim
47 words
A method in accordance with claim 7 wherein said second V T implant of ions is performed with a dosage of from about 1×10 12 cm -2 to about 3×10 12 cm -2 with an energy within a range from about 40 keV to about 80 keV.
Claim 11
Dependent Claim
45 words
A method in accordance with claim 8 wherein said PMOS punchthrough voltage implant of ions comprises a double charge with a dose from about 2.4×10 12 to about 4×10 12 , with an energy within a range from about 380 keV to about 400 keV.
Claim 12
Dependent Claim
27 words
A method in accordance with claim 9 wherein said retrograde implant dopant comprises BF 2 + ions and said punchthrough implant dopant comprises 31 P +2 ions.
References Cited (Backward Citations)
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