US5392297A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for automatic isolation of functional blocks within integrated circuits
Assignee: Philips Semiconductors Inc
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Filing: 1992-06-05
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Granted: 1995-02-21
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Expires: 2012-06-05
Abstract
Abstract A system for generating configurations for isolation circuits that can be designed into ASIC chips such that the isolation circuits are transparent during normal operation of the host chip but allow the embedded functional blocks to be readily isolated and accessed for testing via the host chip's pads.
Inventors
- 👤 Martin J. Bell
- 👤 Muhammad A. Samad
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:22
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318505; G06; G06F; G06F11/00; G06F11/22; G06F11/2273
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
250 words
A method of sequentially testing a plurality of functional blocks having data ports within an integrated circuit having external circuit connectors using isolation circuits that are substantially transparent during normal operation of the integrated circuit, comprising the steps of: a) assigning designations to the functional blocks to be tested; b) selecting the external circuit connectors of the integrated circuit to which respective ports of each of the functional blocks to be tested are to be connected for testing; c) for each selected external connector, embedding a first multiplexer in the integrated circuit for multiplexing system signals in the integrated circuit with test signals associated with testing the functional blocks, said first multiplexer having a select port; d) controlling the select port of the first multiplexer with a signal which identifies whether or not the integrated circuit is in a test mode; e) for each selected pad and each set of two or more functional blocks that are to be connected to the pad for testing, embedding in the integrated circuit a second multiplexer circuit having a select port and an output port, with the output of the second multiplexer circuit connected to the first multiplexer; and f) simultaneous with step d), controlling the select port of the second multiplexer circuit with a signal which uniquely identifies the functional block to be tested; whereby each functional block, when identified as the functional block to be tested, is connected through said first and second multiplexers directly to a selected external circuit connector.
Claim 2
Independent Claim
250 words
A method of sequentially testing a plurality of functional blocks having data ports within an integrated circuit having external circuit connectors using isolation circuits that are substantially transparent during normal operation of the integrated circuit, comprising the steps of: a) assigning designations to the functional blocks to be tested; b) selecting the external circuit connectors of the integrated circuit to which respective ports of each of the functional blocks to be tested are to be connected for testing; c) for each selected external connector, embedding a first multiplexer in the integrated circuit for multiplexing system signals in the integrated circuit with test signals associated with testing the functional blocks, said first multiplexer having a select port; d) controlling the select port of the first multiplexer with a signal which identifies whether or not the integrated circuit is in a test mode; e) for each selected pad and each set of two or more functional blocks that are to be connected to the pad for testing, embedding in the integrated circuit a second multiplexer circuit having a select port and an output port, with the output of the second multiplexer circuit connected to the first multiplexer; and f) simultaneous with step d), controlling the select port of the second multiplexer circuit with a signal which uniquely identifies the functional block to be tested; whereby each functional block, when identified as the functional block to be tested, is connected through said first and second multiplexers directly to a selected external circuit connector.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-20 | 1998-08-22 | 1999-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-20 | 2002-08-22 | 2003-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-20 | 2006-08-22 | 2007-02-21 | $7700.00 | Window Closed / Lapsed |