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US5391979A Expired / Lapsed US ⏱️ 0.0 years remaining

Constant current generating circuit for semiconductor devices

Assignee: Mitsubishi Electric Corp
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Filing: 1993-10-13
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Granted: 1995-02-21
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Expires: 2013-10-13
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Abstract

Abstract The constant current generating circuit includes a high resistance element for generating a very small current. This very small current is supplied to a first MOS transistor having a sufficiently large gate width to gate length ratio. The gate-source voltage of the first MOS transistor becomes its threshold voltage VTH, and the voltage applied across a resistance connected between the gate of the first MOS transistor and the ground line is set to a constant value VTH. Thus, a constant current is normally passed through the resistance. Since the very small current is supplied from the high resistance element which is normally turned on, regardless of the change of the power supply voltage, a constant current can be generated stably.

Inventors

  • 👤 Takeshi Kajimoto
  • 👤 Takayuki Miyamoto

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 20:12
CPC Classifications
H; H03; H03K; H03K19/00; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/30; G11; G11C; G11C5/00; G11C5/14

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 157 words
A constant current generating circuit, comprising: a first resistive means having a first end connected to a first power supply and a second end, for supplying a small current flow; a first insulated gate type field effect transistor having a first conduction terminal connected to said second end of said first resistive means, a second conduction terminal connected to a second power supply, and a control terminal, capable of supplying a large current flow; a second resistive element having a first end connected to said control terminal of said first insulated gate type field effect transistor and a second end connected to said second power supply; and a second insulated gate-type field effect transistor having a control electrode connected to said first conduction terminal of said first insulated gate type field effect transistor, a first conduction terminal connected to said first end of said second resistive element, and a second conduction terminal connected to an output node.
Claim 2
Dependent Claim 157 words
A constant current generating circuit, comprising: a first resistive means having a first end connected to a first power supply and a second end, for supplying a small current flow; a first insulated gate type field effect transistor having a first conduction terminal connected to said second end of said first resistive means, a second conduction terminal connected to a second power supply, and a control terminal, capable of supplying a large current flow; a second resistive element having a first end connected to said control terminal of said first insulated gate type field effect transistor and a second end connected to said second power supply; and a second insulated gate-type field effect transistor having a control electrode connected to said first conduction terminal of said first insulated gate type field effect transistor, a first conduction terminal connected to said first end of said second resistive element, and a second conduction terminal connected to an output node.
Claim 3
Dependent Claim 27 words
The circuit according to claim 1, wherein said first resistive element comprises an insulated gate type transistor having a control gate connected to said second power supply.
Claim 4
Dependent Claim 39 words
The circuit according to claim 1, wherein said first resistive element comprises an insulated gate type transistor having a first conduction terminal connected to said first power supply, and a control gate and a second conduction terminal connected together.
Claim 5
Dependent Claim 25 words
The circuit according to claim 1, wherein said first resistive element has a smaller conductance than said first insulated gate type field effect transistor has.
Claim 6
Dependent Claim 39 words
The circuit according to claim 1, wherein said first resistive element includes an insulated gate type field effect transistor having a smaller gate width to gate length ratio than that of said first insulated gate type field effect transistor.
Claim 7
Dependent Claim 42 words
The circuit according to claim 1, further comprising a current mirror component coupled to said output node for supplying to another output node a current flow corresponding to a current flow amount flowing through said second insulated gate type field effect transistor.
Claim 8
Dependent Claim 23 words
The circuit according to claim 6, further comprising a third resistive element connected between said another output node and said second power supply.
Claim 9
Dependent Claim 20 words
The circuit according to claim 7, wherein said second resistive element comprises a polysilicon resistance having a trimmable resistance value.
Claim 10
Dependent Claim 55 words
The circuit according to claim 7, wherein said second resistive element includes a plurality of polysilicon resistors connected in series between said second power supply and said control terminal of said first transistor, and a plurality of fusible link elements provided corresponding to said plurality of polysilicon resistors and in parallel with corresponding polysilicon resistors.
Claim 11
Dependent Claim 25 words
The circuit according to claim 7, wherein said third resistive element comprises a resistor-connected insulated gate type field effect transistor having a trimmable resistance value.
Claim 12
Dependent Claim 82 words
The circuit according to claim 7, wherein said third resistive element includes a plurality of insulated gate type field effect transistors connected in series between said second power supply and said additional output node, each of said plurality of insulated gate type having a control gate connected to said second power supply, and a plurality of fusible link element provided corresponding to said plurality of insulated gate type field effect transistors and in parallel with corresponding insulated gate type field effect transistors.
Claim 13
Dependent Claim 138 words
A circuit for generating a reference current flow at an output node, comprising: a first resistance element having a first end connected to receive a first power supply voltage, for constantly supplying a small current flow therethrough in operation; a second resistance element having an end connected to receive a second power supply voltage; a transistor element having a threshold voltage and responsive to said small current flow of said first resistance element for applying a voltage of said threshold voltage across said second resistance element; and an element provided between said output node and said second resistance element, for absorbing a potential change at said output node to cause a constant current flow flowing through said second resistance element, in response to a potential difference between another end of said first resistance element and said output node.
Claim 14
Dependent Claim 138 words
A circuit for generating a reference current flow at an output node, comprising: a first resistance element having a first end connected to receive a first power supply voltage, for constantly supplying a small current flow therethrough in operation; a second resistance element having an end connected to receive a second power supply voltage; a transistor element having a threshold voltage and responsive to said small current flow of said first resistance element for applying a voltage of said threshold voltage across said second resistance element; and an element provided between said output node and said second resistance element, for absorbing a potential change at said output node to cause a constant current flow flowing through said second resistance element, in response to a potential difference between another end of said first resistance element and said output node.

References Cited (Backward Citations)

US4322676A Cited
US4527213A Cited
US4771227A Cited
US5278491A Cited
US5315230A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-02-20 1998-08-22 1999-02-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-02-20 2002-08-22 2003-02-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-02-20 2006-08-22 2007-02-21 $7700.00 Window Closed / Lapsed

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