Patent US5390224A successfully refreshed from Google Patents.
US5390224A
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Clock control apparatus
Assignee: Fujitsu Ltd
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Filing: 1993-09-09
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Granted: 1995-02-14
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Expires: 2013-09-09
Abstract
Abstract A clock control apparatus having a basic period clock and a plurality of clocks with different phases from the basic period clock by t/N period, is used with an information processing unit. The apparatus comprising a clock signal generating portion for generating pulses of the basic period clock, a cycle counter for counting the number of pulses of the basic period clock received from the clock signal generating portion when a start command is received and for outputting a cycle counter clock stop signal when the number of pulses becomes a predetermined count value, a control portion for outputting a basic enable period signal for controlling the basic period clock and a delay enable period signal for controlling the t/N period clocks by a flag and the cycle counter clock stop signal, the flag being assignable before the start command is received, a basic period clock enabling portion for receiving pulses of the basic period clock and for outputting the pulses of the basic period clock for a period designated by the basic enable period signal, and a t/N delay period clock enabling portion for generating pulses of the t/N period clocks and for outputting the pulses for a period designated by the delay enable period signal.
Inventors
- 👤 Hiroshi Komatsuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 22:28
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
208 words
A clock control apparatus having a basic period clock (t) and a plurality of clocks with different phases from said basic period clock by t/N period, for use with an information processing unit, said apparatus comprising: a clock signal generating means for generating pulses of said basic period clock; a cycle counter for counting the number of pulses of said basic period clock received from said clock signal generating means when a start command is received and for outputting a cycle counter clock stop signal when the number of pulses becomes a predetermined count value; a control means for outputting a basic enable period signal for controlling said basic period clock and a delay enable period signal for controlling said t/N period clocks by a flag and said cycle counter clock stop signal, said flag being pre-assignable before said start command is received; a basic period clock enabling means for receiving pulses of said basic period clock and for outputting the pulses of said basic period clock for a period designated by said basic enable period signal; and a t/N delay period clock enabling means for generating pulses of said t/N period clocks and for outputting the pulses for a period designated by said delay enable period signal.
Claim 2
Dependent Claim
208 words
A clock control apparatus having a basic period clock (t) and a plurality of clocks with different phases from said basic period clock by t/N period, for use with an information processing unit, said apparatus comprising: a clock signal generating means for generating pulses of said basic period clock; a cycle counter for counting the number of pulses of said basic period clock received from said clock signal generating means when a start command is received and for outputting a cycle counter clock stop signal when the number of pulses becomes a predetermined count value; a control means for outputting a basic enable period signal for controlling said basic period clock and a delay enable period signal for controlling said t/N period clocks by a flag and said cycle counter clock stop signal, said flag being pre-assignable before said start command is received; a basic period clock enabling means for receiving pulses of said basic period clock and for outputting the pulses of said basic period clock for a period designated by said basic enable period signal; and a t/N delay period clock enabling means for generating pulses of said t/N period clocks and for outputting the pulses for a period designated by said delay enable period signal.
Claim 3
Dependent Claim
24 words
The apparatus as set forth in claim 1, wherein said cycle counter is adapted to automatically stop when the count value thereof becomes "0".
Claim 4
Dependent Claim
39 words
The apparatus as set forth in claim 1, wherein said cycle counter comprises a counter for decrementing a predetermined value by N corresponding to the number of pulses of said basic period clock received from said clock generating means.
Claim 5
Dependent Claim
64 words
The apparatus as set forth in claim 1, wherein said cycle counter comprises a clock control circuit for decrementing a predetermined value by N corresponding to the number of pulses of said basic period clock received from said clock generating means and for outputting said cycle counter clock stop signal when the count value becomes a value in the range from 1 to N.
Claim 6
Dependent Claim
39 words
The apparatus as set forth in claim 1, wherein said cycle counter comprises a counter for incrementing a predetermined value by N corresponding to the number of pulses of said basic period clock received from said clock generating means.
Claim 7
Dependent Claim
64 words
The apparatus as set forth in claim 1, wherein said control means comprises a clock stop setting means for generating a clock stop signal, said clock stop signal being enabled by an external stop command, the enable of said clock stop signal being disabled by a start request, said disable being enabled by said cycle counter clock stop signal received from said cycle counter.
Claim 8
Dependent Claim
31 words
The apparatus as set forth in claim 1, wherein said control means comprises a clock stop delay means for shifting said clock stop signal by pulses of said basic period clock.
Claim 9
Dependent Claim
166 words
The apparatus as set forth in claim 1, wherein when the count value of said cycle counter is an odd number and the value of said flag is "1", said control means being adapted to enable said delay enable period signal and then said basic enable period signal with a delay of one clock cycle and to disable both said basic enable period signal and said delay enable period signal at the same time after said cycle counter clock stop signal is received from said cycle counter; and wherein when the count value of said cycle counter is an odd number and the value of said flag is "0", said control means being adapted to enable both said basic enable period signal and said delay enable period signal at the same time and to disable said delay enable period signal and then said basic enable period signal with a delay of one clock cycle after said cycle counter stop signal is received from said cycle counter.
Claim 10
Dependent Claim
167 words
The apparatus as set forth in claim 1, wherein when the count value of said cycle counter is an even number and the value of said flag is "1", said control means being adapted to enable said delay enable period signal and then said basic enable period signal with a delay of one clock cycle and to disable said delay enable period signal and then said basic enable period signal with a delay of one clock cycle after said cycle counter clock stop signal is received from said cycle Counter; and wherein when the count value of said cycle counter is an even number and the value of said flag is "0", said control means being adapted to enable both said basic enable period signal and said delay enable period signal at the same time and to disable both said delay enable period signal and said basic enable period signal at the same time after said cycle counter clock stop signal is received from said cycle counter.
Claim 11
Dependent Claim
121 words
The apparatus as set forth in claim 1, wherein said control means comprises: a clock stop A/B generating circuit for determining conditions of generating said basic enable period signal and said delay enable period signal; and flip-flops for temporarily storing the determined results of said clock stop A/B generating circuit; wherein when determined results for enabling said basic enable period signal are received from said clock stop generating circuit, said flip-flop is adapted to store said results and to output said basic enable period signal; and wherein when determined results for enabling said delay enable period signal are received from said clock stop generating circuit, said flip-flop is adapted to store said results and to output said delay enable period signal.
Claim 12
Dependent Claim
38 words
The apparatus as set forth in claim 1, wherein said basic period clock enabling means is adapted to OR a signal of said basic period clock and said basic enable period signal and to output the resultant signal.
Claim 13
Dependent Claim
39 words
The apparatus as set forth in claim 1, wherein said t/N delay period clock enabling means is adapted to OR a pulse of said basic period clock and said deldelay enable period signal so as to control said clock.
Claim 14
Dependent Claim
43 words
The apparatus as set forth in claim 1, wherein said t/N delay period clock enabling means is adapted to OR a pulse of said basic period clock and said delay enable period signal and to delay the ORed result by a delay line.
Claim 15
Dependent Claim
50 words
The apparatus as set forth in claim 1, further comprising a gate circuit for ORing the output of said basic period clock enabling means and the output of said t/N delay period clock enabling means and for outputting a clock signal with twice higher period than said basic period clock.
Claim 16
Dependent Claim
56 words
The apparatus as set forth in claim 1, further comprising a gate circuit for ORing the output of said basic period clock enabling means and the output of said t/N delay period clock enabling means and for outputting a clock signal with n (where n is any integer) times higher period than said basic period clock.
Claim 17
Dependent Claim
24 words
The apparatus as set forth in claim 1, wherein said t/N delay period clock enabling means is adapted to perform a t/2 delay operation.
Claim 18
Dependent Claim
37 words
The apparatus as set forth in claim 1, wherein said t/N delay period clock enabling means is adapted to generate output signals with a plurality of phases with delays of Mt/N period (where M is any number).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-13 | 1998-08-15 | 1999-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-13 | 2002-08-15 | 2003-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-13 | 2006-08-15 | 2007-02-14 | $7700.00 | Window Closed / Lapsed |