US5390195A
Expired / Lapsed
US
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Miller-squared decoder with erasure flag output
Assignee: Ampex Corp
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Filing: 1992-04-03
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Granted: 1995-02-14
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Expires: 2012-04-03
Abstract
Abstract A method and apparatus for the generation of a signal flag in response to illegal channel code patterns from an information channel, the signal flag may typically be used as an erasure flag by a subsequent error correction decoder. This erasure flag, being indicative of a data error position which can then be fed into a utilization circuit such as an error correction logic for performance improvement. In particular, a Miller-squared channel code format decoder in accordance with the present invention can easily and inexpensively provide error position information thereby enhancing error correction power, such as that of a Reed-Solomon error correction code.
Inventors
- 👤 Richard K. Brush
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:26
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1833; G11B20/14; G11B20/1403; G11B20/1423; H; H03; H03M; H03M13/00; H03M13/31; H03M5/00; H03M5/02; H03M5/04; H03M5/14
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
207 words
A decoder in a transmission system for converting an encoded input serial data stream into an output data stream, said input data stream being encoded according to at least two coding formats, one such coding format, a channel code, enabling said input serial data stream to be generally free of any net DC component and another such coding format, an error correction code providing data redundancy to said input data stream, said decoder comprising: means for receiving said input data stream; means for decoding serially said input data stream according to said channel code for generating a first data stream generally representative of said input data stream; means for determining if said input data stream conforms to said channel code; means responsive to said determining means for generating a signal indicative of a violation of said channel code arising from a data error; means for transmitting said signal in synchronism with said first data stream, said signal being indicative of one or more data bit locations at which a data error occurs in said first data stream; and other means responsive to said signal and said first data stream for decoding said first data stream according to said error correction code for generating said output data stream.
Claim 2
Dependent Claim
207 words
A decoder in a transmission system for converting an encoded input serial data stream into an output data stream, said input data stream being encoded according to at least two coding formats, one such coding format, a channel code, enabling said input serial data stream to be generally free of any net DC component and another such coding format, an error correction code providing data redundancy to said input data stream, said decoder comprising: means for receiving said input data stream; means for decoding serially said input data stream according to said channel code for generating a first data stream generally representative of said input data stream; means for determining if said input data stream conforms to said channel code; means responsive to said determining means for generating a signal indicative of a violation of said channel code arising from a data error; means for transmitting said signal in synchronism with said first data stream, said signal being indicative of one or more data bit locations at which a data error occurs in said first data stream; and other means responsive to said signal and said first data stream for decoding said first data stream according to said error correction code for generating said output data stream.
Claim 3
Dependent Claim
14 words
The decoder according to claim 1 wherein said signal is an erasure flag signal.
Claim 4
Dependent Claim
27 words
The decoder according to claim 1 wherein said signal is a pulse, the initiation and duration are indicative of said data error in said input data stream.
Claim 5
Dependent Claim
29 words
The decoder according to claim 3 wherein said signal is further indicative of two likely data bits in said first data stream one of which contains said data error.
Claim 6
Dependent Claim
44 words
The decoder according to claim 1 wherein said signal, indicative of said channel code violation having a pulse sequence in said input data stream, said signal departs said decoding means simultaneously with a portion of said first data stream representative of said pulse sequence.
Claim 7
Dependent Claim
17 words
The decoder according to claim 1 wherein said signal is output separately from said first data stream.
Claim 8
Dependent Claim
153 words
A decoder for converting a serially clocked and encoded input binary data stream into an output data stream, said input data stream being encoded according to the Miller-squared (M 2 ) channel code and according to a data error correction code, said decoder comprising: decoding means for said input data stream for generating a first data stream; detection means for identifying data sequences in said input data stream not conforming to said M 2 channel code; indication means responsive to said data sequences for producing signal flags indicative of data error positions, said signal flags in synchronism with said first data stream and simultaneously with a portion of said first data stream representative of said data sequences in said input data stream; and other means responsive to said signal and said first data stream for decoding said first data stream according to said data error correction code for generating said output data stream.
Claim 9
Dependent Claim
153 words
A decoder for converting a serially clocked and encoded input binary data stream into an output data stream, said input data stream being encoded according to the Miller-squared (M 2 ) channel code and according to a data error correction code, said decoder comprising: decoding means for said input data stream for generating a first data stream; detection means for identifying data sequences in said input data stream not conforming to said M 2 channel code; indication means responsive to said data sequences for producing signal flags indicative of data error positions, said signal flags in synchronism with said first data stream and simultaneously with a portion of said first data stream representative of said data sequences in said input data stream; and other means responsive to said signal and said first data stream for decoding said first data stream according to said data error correction code for generating said output data stream.
Claim 10
Dependent Claim
32 words
The decoder according to claim 7 wherein said first data stream includes binary data in Non-Return-To-Zero (NRZ) format having a NRZ clock at half of the Miller-squared (M 2 ) clock frequency.
Claim 11
Dependent Claim
49 words
The decoder according to claim 7 having said input data stream clocked by a Miller-squared (M 2 ) frequency waveform wherein said data sequences include two consecutive signal phase transitions in said input data stream spanning less than two clock periods as defined by said M 2 clock frequency.
Claim 12
Dependent Claim
49 words
The decoder according to claim 7 having said input data stream clocked by a Miller-squared (M 2 ) frequency waveform wherein said data sequences include two consecutive signal phase transitions in said input data stream spanning greater than six clock periods as defined by said M 2 clock frequency.
Claim 13
Dependent Claim
85 words
The decoder according to claim 7 having said input data stream clocked by a Miller-squared (M 2 ) frequency waveform wherein said data sequences include a first signal phase transition in said input data stream occurring between data cells as defined by said M 2 clock frequency and a successive second signal phase transition in said input data stream occurring subsequent to said first signal phase transition, both signal phase transitions spanning at least four clock periods as defined by said M 2 clock frequency.
Claim 14
Dependent Claim
16 words
The decoder according to claim 7 wherein said data error correction code includes a Reed-Solomon code.
Claim 15
Dependent Claim
167 words
A decoder receiving from a transmission channel according to a channel code a self-clocking encoded binary data signal sequentially in successive clocked bit cells modified to remove any net DC component in an otherwise normal transmission having logical first bit states normally transmitted as signal phase transitions relatively early in respective bit cells and logical second bit states normally transmitted as signal phase transitions relatively late in respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed, said decoder comprising: means for decoding said binary data signal for generating a first data stream; detection means for identifying data sequences in said binary data signal not conforming to said channel code; and indication means responsive to said data sequences for producing signal flags indicative of data error positions, said signal flags in synchronism with said first data stream and simultaneously with a portion of said first data stream representative of said data sequences.
Claim 16
Dependent Claim
167 words
A decoder receiving from a transmission channel according to a channel code a self-clocking encoded binary data signal sequentially in successive clocked bit cells modified to remove any net DC component in an otherwise normal transmission having logical first bit states normally transmitted as signal phase transitions relatively early in respective bit cells and logical second bit states normally transmitted as signal phase transitions relatively late in respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed, said decoder comprising: means for decoding said binary data signal for generating a first data stream; detection means for identifying data sequences in said binary data signal not conforming to said channel code; and indication means responsive to said data sequences for producing signal flags indicative of data error positions, said signal flags in synchronism with said first data stream and simultaneously with a portion of said first data stream representative of said data sequences.
Claim 17
Dependent Claim
18 words
The decoder according to claim 13 wherein said first data stream includes binary data in Non-Return-To-Zero (NRZ) format.
Claim 18
Dependent Claim
47 words
The decoder according to claim 13 having said binary data signal clocked at a frequency according to said channel code wherein said data sequences include two consecutive signal phase transitions in said binary data signal spanning less than two clock periods as defined by said clock frequency.
Claim 19
Dependent Claim
47 words
The decoder according to claim 13 having said binary data signal clocked at a frequency according to said channel code wherein said data sequences include two consecutive signal phase transitions in said binary data signal spanning greater than six clock periods as defined by said clock frequency.
Claim 20
Dependent Claim
81 words
The decoder according to claim 13 having said binary data signal clocked at a frequency according to said channel code wherein said data sequences include a first signal phase transition in said binary data signal occurring between bit cells as defined by said clock frequency and a successive second signal phase transition in said binary data signal occurring subsequent to said first signal phase transition, both signal phase transitions spanning at least four clock periods as defined by said clock frequency.
Claim 21
Dependent Claim
200 words
A decoding method in a transmission system for converting an encoded input serial data stream into an output data stream, said input data stream being encoded according to at least two coding formats, one such coding format, a channel code, enabling said input serial data stream to be generally free of any net DC component and another such coding format, an error correction code providing data redundancy to said input data stream, said method comprising the steps of: receiving said input data stream; decoding serially said input data stream according to said channel code for generating a first data stream generally representative of said input data stream; determining if said input data stream conforms to said channel code; generating in response to said determining step a signal indicative of a violation of said channel code arising from a data error; transmitting said signal in synchronism with said first data stream, said signal being indicative of one or more data bit locations at which a data error occurs in said first data stream; and decoding in response to said signal and said first data stream, said first data stream according to said error correction code for generating said output data Stream.
Claim 22
Dependent Claim
200 words
A decoding method in a transmission system for converting an encoded input serial data stream into an output data stream, said input data stream being encoded according to at least two coding formats, one such coding format, a channel code, enabling said input serial data stream to be generally free of any net DC component and another such coding format, an error correction code providing data redundancy to said input data stream, said method comprising the steps of: receiving said input data stream; decoding serially said input data stream according to said channel code for generating a first data stream generally representative of said input data stream; determining if said input data stream conforms to said channel code; generating in response to said determining step a signal indicative of a violation of said channel code arising from a data error; transmitting said signal in synchronism with said first data stream, said signal being indicative of one or more data bit locations at which a data error occurs in said first data stream; and decoding in response to said signal and said first data stream, said first data stream according to said error correction code for generating said output data Stream.
Claim 23
Dependent Claim
15 words
The decoding method according to claim 18 wherein said signal is an erasure flag signal.
Claim 24
Dependent Claim
28 words
The decoding method according to claim 18 wherein said signal is a pulse, the initiation and duration are indicative of said data error in said input data stream.
Claim 25
Dependent Claim
30 words
The decoding method according to claim 20 wherein said signal is further indicative of two likely data bits in said first data stream one of which contains said data error.
Claim 26
Dependent Claim
47 words
The decoding method according to claim 18 wherein said signal, indicative of said channel code violation having a pulse sequence in said input data stream, said transmitting step causing said signal to be simultaneously with a portion of said first data stream representative of said pulse sequence.
Claim 27
Dependent Claim
18 words
The decoding method according to claim 18 wherein said signal is output separately from said first data stream.
Claim 28
Dependent Claim
150 words
A decoding method for converting a serially clocked and encoded input binary data stream into an output data stream, said input data stream being encoded according to the Miller-squared (M 2 ) channel code and according to a data error correction code, said decoding method comprising the steps of: decoding said input data stream for generating a first data stream; identifying data sequences in said input data stream not conforming to said M 2 channel code; indicating responsive to said data sequences for producing signal flags indicative of data error positions, said signal flags in sychronism with said first data stream and simultaneously with a portion of said first data stream representative of said data sequences in said input data stream; and decoding in response to said signal and said first data stream, said first data stream according to said data error correction code for generating said output data stream.
Claim 29
Dependent Claim
150 words
A decoding method for converting a serially clocked and encoded input binary data stream into an output data stream, said input data stream being encoded according to the Miller-squared (M 2 ) channel code and according to a data error correction code, said decoding method comprising the steps of: decoding said input data stream for generating a first data stream; identifying data sequences in said input data stream not conforming to said M 2 channel code; indicating responsive to said data sequences for producing signal flags indicative of data error positions, said signal flags in sychronism with said first data stream and simultaneously with a portion of said first data stream representative of said data sequences in said input data stream; and decoding in response to said signal and said first data stream, said first data stream according to said data error correction code for generating said output data stream.
Claim 30
Dependent Claim
33 words
The decoding method according to claim 24 wherein said first data stream represents binary data in Non-Return-To-Zero (NRZ) format having a NRZ clock at half of the Miller-squared (M 2 ) clock frequency.
Claim 31
Dependent Claim
50 words
The decoding method according to claim 24 having said input data stream clocked by a Miller-squared (M 2 ) frequency waveform wherein said data sequences include two consecutive signal phase transitions in said input data stream spanning less than two clock periods as defined by said M 2 clock frequency.
Claim 32
Dependent Claim
49 words
The decoding method according to claim 24 having said input data stream clocked by a Miller-squared (M 2 ) frequency waveform wherein said data sequences include two consecutive signal phase transitions in said input data stream spanning greater than six clock periods as defined by said M2 clock frequency.
Claim 33
Dependent Claim
85 words
The decoding method according to claim 24 having said input data stream clocked by a Miller-squared (M 2 ) frequency waveform wherein said data sequences include a first signal phase transition in said input data stream occurring between data cells as defined by said M 2 clock frequency and a successive second signal phase transition in said input data stream occurring subsequent to said first signal phase transition, both signal phase transitions spanning at least four clock periods as defined by said M2 clock frequency.
Claim 34
Dependent Claim
170 words
A decoding method processing a self-clocking encoded binary data signal from a transmission channel according to a channel code, said binary data signal traveling sequentially in successive clocked bit cells modified to remove any net DC component in an otherwise normal transmission having logical first bit states normally transmitted as signal phase transitions relatively early in respective bit cells and logical second bit states normally transmitted as signal phase transitions relatively late in respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed, said decoding method comprising the steps of: decoding said binary data signal for generating a first data stream; identifying data sequences in said binary data signal not conforming to said channel code; and indicating in response to said data sequences signal flags indicative of data error position, said signal flags in sychronism with said first data stream and simultaneously with a portion of said first data stream representative of said data sequences.
Claim 35
Dependent Claim
170 words
A decoding method processing a self-clocking encoded binary data signal from a transmission channel according to a channel code, said binary data signal traveling sequentially in successive clocked bit cells modified to remove any net DC component in an otherwise normal transmission having logical first bit states normally transmitted as signal phase transitions relatively early in respective bit cells and logical second bit states normally transmitted as signal phase transitions relatively late in respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed, said decoding method comprising the steps of: decoding said binary data signal for generating a first data stream; identifying data sequences in said binary data signal not conforming to said channel code; and indicating in response to said data sequences signal flags indicative of data error position, said signal flags in sychronism with said first data stream and simultaneously with a portion of said first data stream representative of said data sequences.
Claim 36
Dependent Claim
19 words
The decoding method according to claim 29 wherein said first data stream includes binary data in Non-Return-To-Zero (NRZ) format.
Claim 37
Dependent Claim
48 words
The decoding method according to claim 29 having said binary data signal clocked at a frequency according to said channel code wherein said data sequences include two consecutive signal phase transitions in said binary data signal spanning less than two clock periods as defined by said clock frequency.
Claim 38
Dependent Claim
48 words
The decoding method according to claim 29 having said binary data signal clocked at a frequency according to said channel code wherein said data sequences include two consecutive signal phase transitions in said binary data signal spanning greater than six clock periods as defined by said clock frequency.
Claim 39
Dependent Claim
81 words
The decoding according to claim 29 having said binary data signal clocked at a frequency according to said channel code wherein said data sequences include a first signal phase transition in said binary data signal occurring between bit cells as defined by said clock frequency and a successive second signal phase transition in said binary data signal occurring subsequent to said first signal phase transition, both signal phase transitions spanning at least four clock periods as defined by said clock frequency.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-02-13 | 1998-08-15 | 1999-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-13 | 2002-08-15 | 2003-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-13 | 2006-08-15 | 2007-02-14 | $7700.00 | Window Closed / Lapsed |