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Patent US5390145A successfully refreshed from Google Patents.
US5390145A
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US
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Resonance tunnel diode memory
Assignee: Fujitsu Ltd
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Filing: 1993-12-14
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Granted: 1995-02-14
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Expires: 2013-12-14
Abstract
Abstract A semiconductor memory device including a plurality of bit lines and a plurality of word lines which intersect to form a matrix of cross points. A respective memory cell is disposed at each cross point and corresponds to the respective word line and respective bit line intersecting at the respective cross point. Each memory cell includes a transfer gate having a first current terminal connected to the corresponding bit line and a control terminal connected to the corresponding word line. Each memory cell also includes a pair of serially connected negative differential resistance memory elements having an interconnection node therebetween. The interconnection node is connected to the second current terminal of the transfer gate. A characteristic controlling circuit is coupled to the plurality of bit lines and controls the voltage of each bit line based on whether a respective memory cell corresponding to the respective bit line is selected or not selected, the characteristic controlling circuit including a plurality of negative differential resistance elements respectively corresponding to the plurality of bit lines.
Inventors
- 👤 Yasuhiro Nakasha
- 👤 Yuu Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:40
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/142; G11C11/00; G11C11/21; G11C11/34; G11C11/36; G11C11/38; G11C2211/00; G11C2211/56; G11C2211/561; G11C2211/5614
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
219 words
A semiconductor memory device comprising: a plurality of bit lines; a plurality of word lines which intersect the plurality of bit lines to form a matrix of cross points, each cross point corresponding to an intersection between a respective bit line and respective word line; a plurality of memory cells, a respective memory cell disposed at each cross point and corresponding to the respective word line and respective bit line intersecting at the respective cross point, each memory cell being individually selectable in accordance with voltages on the corresponding bit line and the corresponding word line, each memory cell comprising: a transfer gate having a first current terminal connected to the corresponding bit line, a control terminal connected to the corresponding word line, and a second current terminal, and a pair of serially connected negative differential resistance memory elements having an interconnection node therebetween which is connected to the second current terminal of the transfer gate; and a characteristic controlling circuit which is coupled to the plurality of bit lines and controls the voltage of each bit line based on whether a respective memory cell corresponding to the respective bit line is selected or not selected, the characteristic controlling circuit comprising a plurality of negative differential resistance elements respectively corresponding to, and connected to, the plurality of bit lines.
Claim 2
Dependent Claim
219 words
A semiconductor memory device comprising: a plurality of bit lines; a plurality of word lines which intersect the plurality of bit lines to form a matrix of cross points, each cross point corresponding to an intersection between a respective bit line and respective word line; a plurality of memory cells, a respective memory cell disposed at each cross point and corresponding to the respective word line and respective bit line intersecting at the respective cross point, each memory cell being individually selectable in accordance with voltages on the corresponding bit line and the corresponding word line, each memory cell comprising: a transfer gate having a first current terminal connected to the corresponding bit line, a control terminal connected to the corresponding word line, and a second current terminal, and a pair of serially connected negative differential resistance memory elements having an interconnection node therebetween which is connected to the second current terminal of the transfer gate; and a characteristic controlling circuit which is coupled to the plurality of bit lines and controls the voltage of each bit line based on whether a respective memory cell corresponding to the respective bit line is selected or not selected, the characteristic controlling circuit comprising a plurality of negative differential resistance elements respectively corresponding to, and connected to, the plurality of bit lines.
Claim 3
Dependent Claim
56 words
A semiconductor memory device according to claim 1, wherein each negative differential resistance element of the characteristic controlling circuit has a current level greater than a current level of the pair of negative differential resistance memory elements of the memory cell corresponding to the respective bit line that corresponds to the respective negative differential resistance element.
Claim 4
Dependent Claim
28 words
A semiconductor memory device according to claim 1, wherein the pair of negative differential resistance memory elements of each memory cell is a pair of resonance tunnel diodes.
Claim 5
Dependent Claim
22 words
A semiconductor memory device according to claim 1, wherein the transfer gate of each memory cell is a high electron mobility transistor.
Claim 6
Dependent Claim
53 words
A semiconductor memory device according to claim 3, wherein the transfer gate of each memory cell is a high electron mobility transistor and the pair of negative differential resistance elements of each memory cell is a pair of resonance tunnel diodes formed on one current terminal region of the high electron mobility transistor.
Claim 7
Dependent Claim
41 words
A semiconductor memory device according to claim 1, further comprising a power supply wiring and a ground wiring, the pair of negative differential resistance memory elements of each memory cell being connected between the power supply wiring and the ground wiring.
Claim 8
Dependent Claim
39 words
A semiconductor memory device according to claim 6, wherein each negative differential resistance element of the characteristic controlling circuit is connected between the power supply wiring and the respective bit line corresponding to the respective negative differential resistance element.
Claim 9
Dependent Claim
38 words
A semiconductor memory device according to claim 6, wherein each negative differential resistance element of the characteristic controlling circuit is connected between the respective bit line corresponding to the respective negative differential resistance element and the ground wiring.
Claim 10
Dependent Claim
52 words
A semiconductor memory device according to claim 6, wherein the characteristic controlling circuit comprises, for each bit line, a respective negative differential resistance element connected between the power supply wiring and the respective bit line and a respective negative differential resistance element connected between the respective bit line and the ground wiring.
Claim 11
Dependent Claim
60 words
A semiconductor memory device according to claim 9, further comprising: a respective switching transistor for each bit line, each switching transistor having a control terminal and being connected between the respective bit line and one of the negative differential resistance elements connected to the respective bit line; and a delay circuit connected to the control terminal of each switching transistor.
Claim 12
Dependent Claim
47 words
A semiconductor memory device according to claim 9, wherein each negative differential resistance element of the characteristic controlling circuit has substantially the same peak voltage and current as each negative differential resistance memory element, and has a current level larger than the negative differential resistance memory elements.
Claim 13
Dependent Claim
25 words
A semiconductor memory device according to claim 6, further comprising a respective voltage clamping element connected between each bit line and the ground potential wiring.
Claim 14
Dependent Claim
28 words
A semiconductor memory device according to claim 6, wherein the pair of negative differential resistance memory elements of each memory cell is a pair of resonance tunnel diodes.
Claim 15
Dependent Claim
18 words
A semiconductor memory device according to claim 6, wherein the transfer gate is a high electron mobility transistor.
Claim 16
Dependent Claim
54 words
A semiconductor memory device according to claim 13, wherein the transfer gate of each memory cell is a high electron mobility transistor and the pair of negative differential resistance memory elements of each memory cell is a pair of resonance tunnel diodes formed on one current terminal region of the high electron mobility transistor.
Claim 17
Dependent Claim
51 words
A semiconductor memory device according to claim 1, wherein the characteristic controlling circuit increases the current on a respective bit line when the memory cell corresponding to the respective bit line is selected, in relation to the current on the respective bit line when the corresponding memory cell is not selected.
Claim 18
Dependent Claim
51 words
A semiconductor memory device according to claim 1, wherein the characteristic controlling circuit increases the potential on a respective bit line when the memory cell corresponding to the respective bit line is selected, in relation to the potential on the respective bit line when the corresponding memory cell is not selected.
Claim 19
Dependent Claim
51 words
A semiconductor memory device according to claim 1, wherein the characteristic controlling circuit decreases the current on a respective bit line when the memory cell corresponding to the respective bit line is not selected, in relation to the current on the respective bit line when the corresponding memory cell is selected.
Claim 20
Dependent Claim
51 words
A semiconductor memory device according to claim 1, wherein the characteristic controlling circuit decreases the potential on a respective bit line when the memory cell corresponding to the respective bit line is not selected, in relation to the potential on the respective bit line when the corresponding memory cell is selected.
Claim 21
Dependent Claim
51 words
A semiconductor memory device according to claim 1, wherein the characteristic controlling circuit decreases the potential on a respective bit line when the memory cell corresponding to the respective bit line is selected, in relation to the potential on the respective bit line when the corresponding memory cell is not selected.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-13 | 1998-08-15 | 1999-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-13 | 2002-08-15 | 2003-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-13 | 2006-08-15 | 2007-02-14 | $7700.00 | Window Closed / Lapsed |