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US5388246A
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Arrangement and method of controlling memory access requests in digital data processing system
Assignee: NEC Corp
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Filing: 1993-10-18
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Granted: 1995-02-07
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Expires: 2013-10-18
Abstract
Abstract Before a memory access request is applied to a memory, a request receive signal is generated and applied to a controller. The controller retrieves information from a request information buffer having a limited memory space. The information is to be returned to a unit which has issued the request and is stored in a reply buffer. The transfer of the information into the reply buffers induces the acceptance of a new request before the completion of the actual access to the memory.
Inventors
- 👤 Hiroyuki Kasai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:37
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1689
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
210 words
A memory access request controller which is provided between a plurality of I/O device controllers and a main memory, said plurality of I/0 device controllers operating under first clocks while said main memory operating under second clocks, said memory access request controller including a buffer which stores memory access request information which includes memory access data and request issued I/O device controller information and request ordered I/O device information, said memory access request information being applied from at least one of said I/0 device controllers, said memory access request controller further comprising: first means, operating under said first clocks, for controlling read/write operations of said buffer; second means, operating under said second clocks and coupled to said first means and said main memory, for receiving said memory access data and said request issued I/O device controller information from said buffer and for generating access request receive information including said request issued I/O device controller information; and third means, coupled to said buffer and said first means and said second means and operating under said first clocks for inducing said first means to transfer said request ordered I/O device information stored in said buffer into said third means in response to said access request receive information received from said second means.
Claim 2
Dependent Claim
210 words
A memory access request controller which is provided between a plurality of I/O device controllers and a main memory, said plurality of I/0 device controllers operating under first clocks while said main memory operating under second clocks, said memory access request controller including a buffer which stores memory access request information which includes memory access data and request issued I/O device controller information and request ordered I/O device information, said memory access request information being applied from at least one of said I/0 device controllers, said memory access request controller further comprising: first means, operating under said first clocks, for controlling read/write operations of said buffer; second means, operating under said second clocks and coupled to said first means and said main memory, for receiving said memory access data and said request issued I/O device controller information from said buffer and for generating access request receive information including said request issued I/O device controller information; and third means, coupled to said buffer and said first means and said second means and operating under said first clocks for inducing said first means to transfer said request ordered I/O device information stored in said buffer into said third means in response to said access request receive information received from said second means.
Claim 3
Dependent Claim
107 words
A memory access request controller as claimed in claim 1 wherein said third means comprises: a reply controller coupled to said second means for receiving said access request receive information and generating a signal in response thereto; a reply buffer coupled to said buffer and said reply controller for storing said request ordered I/O device information; and a counter, provided between said first means and said reply controller, for counting up each time said first means stores said memory access request information in said buffer and for counting down in response to said signal generated by said reply controller in response to said access request receive information.
Claim 4
Independent Claim
181 words
A method of controlling memory access requests using a controller which is provided between a plurality of I/O device controllers and a main memory, said plurality of I/O device controllers operating under first clocks while said main memory operating under second clocks, said controller including a buffer which stores memory access request information which includes memory access data and request issued I/O device controller information and request ordered I/O device information, said memory access request information being applied from at least one of said I/O device controllers, said method comprising the steps of: (a) storing said memory access request information in said buffer under operation of said first clocks; (b) receiving said memory access data and said request issued I/O device controller information from said buffer under operation of said second clocks and generating access request receive information including said request issued I/O device controller information under operation of said second clocks; and (c) inducing storage of said request ordered I/O device information stored in said buffer in response to said access request receive information under operation of said first clocks.
Claim 5
Independent Claim
181 words
A method of controlling memory access requests using a controller which is provided between a plurality of I/O device controllers and a main memory, said plurality of I/O device controllers operating under first clocks while said main memory operating under second clocks, said controller including a buffer which stores memory access request information which includes memory access data and request issued I/O device controller information and request ordered I/O device information, said memory access request information being applied from at least one of said I/O device controllers, said method comprising the steps of: (a) storing said memory access request information in said buffer under operation of said first clocks; (b) receiving said memory access data and said request issued I/O device controller information from said buffer under operation of said second clocks and generating access request receive information including said request issued I/O device controller information under operation of said second clocks; and (c) inducing storage of said request ordered I/O device information stored in said buffer in response to said access request receive information under operation of said first clocks.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-06 | 1998-08-08 | 1999-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-06 | 2002-08-08 | 2003-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-06 | 2006-08-08 | 2007-02-07 | $7700.00 | Window Closed / Lapsed |