Data security arrangements for semiconductor programmable devices

Claim 2

A programmable logic device comprising a semiconductor device having (1) configurable circuitry that configures itself in accordance with data, (2) an input circuit for receiving encrypted data, said encrypted data being used to determine configuration of said configurable circuitry, (3) decrypting circuitry connected to said input circuit to decrypt said encrypted data, (4) a non-volatile data storage device connected to said decrypting circuitry and holding a key value for use in decrypting said encrypted data, and (5) volatile storage circuitry connected both to said decrypting circuitry for receiving decrypted data from the decrypting circuitry and to said configurable circuitry whereby the configurable circuitry is configured in accordance with said decrypted data.

Claim 3

Circuit configuration apparatus comprising a programmable logic device and encrypting circuitry for providing encrypted circuit configuration data, said programmable logic device comprising a semiconductor device having configurable circuitry that configures itself in accordance with data, an input circuit for receiving encrypted data, said encrypted data being used to determine the configuration of said configurable circuitry, decrypting circuitry connected to said input circuit to decrypt said encrypted data, a non-volatile data storage device connected to said decrypting circuitry and holding a key value for use in decrypting said encrypted data, and volatile storage circuitry connected both to said decrypting circuitry for receiving decrypted data from the decrypting circuitry and to said configurable circuitry whereby the configurable circuitry is configured in accordance with said decrypted data and said encrypting circuitry having a first input circuit for receiving a key value which is the same as said key value for the programmable logic device, a second input circuit for receiving data defining circuit configuration of the programmable logic device, an output circuit for outputting said data in encrypted form, and a storage device for storing said data in encrypted form, said storage device having output circuitry for connection to said input circuit of said programmable logic device.

Claim 4

Circuit configuration apparatus comprising a programmable logic device and encrypting circuitry for providing encrypted circuit configuration data, said programmable logic device comprising a semiconductor device having configurable circuitry that configures itself in accordance with data, an input circuit for receiving encrypted data, said encrypted data being used to determine the configuration of said configurable circuitry, decrypting circuitry connected to said input circuit to decrypt said encrypted data, a non-volatile data storage device connected to said decrypting circuitry and holding a key value for use in decrypting said encrypted data, and volatile storage circuitry connected both to said decrypting circuitry for receiving decrypted data from the decrypting circuitry and to said configurable circuitry whereby the configurable circuitry is configured in accordance with said decrypted data and said encrypting circuitry having a first input circuit for receiving a key value which is the same as said key value for the programmable logic device, a second input circuit for receiving data defining circuit configuration of the programmable logic device, an output circuit for outputting said data in encrypted form, and a storage device for storing said data in encrypted form, said storage device having output circuitry for connection to said input circuit of said programmable logic device.

Claim 5

Circuit configuration apparatus as claimed in claim 2, wherein the encrypting circuitry and the decrypting circuitry each include a pseudo-random sequence generator.

Claim 6

Circuit configuration apparatus as claimed in claim 3, wherein the pseudo-random sequence generator comprises a 31-bit maximal length shift register which generates a pseudo-random sequence that is 2,147,483,647 bits in overall length.

Claim 7

Circuit configuration apparatus as claimed in claim 4, wherein the maximal length shift register has a preloaded signal and a data input terminal.

Claim 8

Circuit configuration apparatus as claimed in claim 5, wherein bit 28 and bit 31 output terminals of the maximal length shift register are connected to an input terminal of an EXCLUSIVE-OR logic circuit whose output terminal is connected to the data input terminal of the maximal length shift register.

Claim 9

Circuit configuration apparatus as claimed in claim 5, wherein the maximal length shift register is forced to start the pseudo-random sequence at a particular point in the sequence by the application of a predetermined sequence start encrypt comprised of a 31 bit preloaded key value.

Claim 10

Circuit Configuration apparatus as claimed in claim 7, wherein the application of the sequence start code to the maximal length shift register in the encrypting circuitry is provided from a keyboard or from a secure file.

Claim 11

Circuit configuration apparatus as claimed in claim 7, wherein the application of the sequence start code to the maximal shift register in the decrypting circuitry is provided from a non-volatile memory within the programmable logic device.

Claim 12

Circuit configuration apparatus as claimed in claim 4, wherein the originating operating data is circuit configuration data and wherein in the encrypting circuitry the circuit configuration data and the pseudo-random sequence are provided to an EXCLUSIVE-OR logic circuit which produces encrypted circuit configuration data.

Claim 13

Circuit configuration apparatus as claimed in claim 10, wherein the pseudo-random sequence and the encrypted circuit configuration data are applied to an EXCLUSIVE-OR logic circuit in the decrypting circuitry to provide decrypted circuit configuration data.

Claim 14

Circuit configuration apparatus as claimed in claim 2, wherein the storage device for encrypted data comprises a read only memory.

Claim 15

Circuit configuration apparatus as claimed in claim 2, wherein the volatile storage circuitry comprises static random access memories.