Non-volatile semiconductor memory device with high voltage generator

Claim 2

A semiconductor integrated circuit device comprising: voltage dropping means for dropping a power source voltage; voltage limiting means having two ends one of which is connected to an output terminal of said voltage dropping means, for limiting an output voltage of said voltage dropping means to a given value; voltage setting means, connected to the other end of said voltage limiting means, for arbitrarily adjusting a voltage at said other end of said voltage limiting means; and a plurality of memory cells each constituted of an erasable and programmable MOSFET having a floating gate and a control gate which is supplied with a voltage appearing on said output terminal of said voltage dropping means.

Claim 3

The semiconductor integrated circuit device according to claim 1, wherein said voltage limiting means comprises one or more Zener diodes connected in series.

Claim 4

The semiconductor integrated circuit device according to claim 2, wherein a Zener breakdown voltage of said Zener diodes is set in a range from 4 V to 7 V.

Claim 5

The semiconductor integrated circuit device according to claim 1, wherein said voltage setting means comprises: voltage generating means for generating an arbitrary voltage having a value between said other end of said voltage limiting means and a reference voltage; voltage comparing means for receiving said arbitrary voltage generated by said voltage generating means as one input; comparison-voltage generating means for generating a comparison voltage to be supplied as an other input of said voltage comparing means; and a MOS type switching element which has a current path inserted between said other end of said voltage limiting means and said reference voltage and whose gate is controlled by a comparison output of said voltage comparing means.

Claim 6

The semiconductor integrated circuit device according to claim 4, wherein said voltage generating means comprises: a plurality of resistors inserted in series between said other end of said voltage limiting means and said reference voltage; and a plurality of voltage selecting means for selecting voltages appearing at nodes between said series-connected resistors in accordance with a control signal.

Claim 7

The semiconductor integrated circuit device according to claim 5, wherein each of said plurality of voltage selecting means is constituted of a transfer gate.

Claim 8

A semiconductor integrated circuit device comprising: a first high voltage generator for generating a first high voltage, said first high voltage generator having a first oscillation circuit, first booster means for boosting a power source voltage based on an oscillation signal generated by said first oscillation circuit, first voltage limiting means having two ends one of which is connected to an output terminal of said first booster means, for limiting an output voltage of said first booster means to a given value, and first voltage setting means, connected to the other end of said first voltage limiting means, for arbitrarily adjusting a voltage at said other end of said first voltage limiting means; a second high voltage generator for generating a second high voltage, said second high voltage generator having a second oscillation circuit, second booster means for boosting said power source voltage based on an oscillation signal generated by said second oscillation circuit, second voltage limiting means having two ends one of which is connected to an output terminal of said second booster means, for limiting an output voltage of said second booster means to a given value, and second voltage setting means, connected to the other end of said second voltage limiting means, for arbitrarily adjusting a voltage at said other end of said second voltage limiting means; a plurality of NAND cells each having a plurality of series-connected MOSFETs each having a floating gate and a control gate; a bit line to which one end of each of said plurality of NAND cells is commonly connected; a plurality of word lines to which said control gates of said memory cells of each of said plurality of NAND cells are respectively connected; address decoding means for receiving said first high voltage generated by said first high voltage generator and an address input and selectively supplying said first high voltage to said plurality of word lines in accordance with said address input; and bit-line voltage supplying means for supplying one of said second high voltage generated by said second high voltage generator and said source voltage to said bit line.

Claim 9

A semiconductor integrated circuit device comprising: a first high voltage generator for generating a first high voltage, said first high voltage generator having a first oscillation circuit, first booster means for boosting a power source voltage based on an oscillation signal generated by said first oscillation circuit, first voltage limiting means having two ends one of which is connected to an output terminal of said first booster means, for limiting an output voltage of said first booster means to a given value, and first voltage setting means, connected to the other end of said first voltage limiting means, for arbitrarily adjusting a voltage at said other end of said first voltage limiting means; a second high voltage generator for generating a second high voltage, said second high voltage generator having a second oscillation circuit, second booster means for boosting said power source voltage based on an oscillation signal generated by said second oscillation circuit, second voltage limiting means having two ends one of which is connected to an output terminal of said second booster means, for limiting an output voltage of said second booster means to a given value, and second voltage setting means, connected to the other end of said second voltage limiting means, for arbitrarily adjusting a voltage at said other end of said second voltage limiting means; a plurality of NAND cells each having a plurality of series-connected MOSFETs each having a floating gate and a control gate; a bit line to which one end of each of said plurality of NAND cells is commonly connected; a plurality of word lines to which said control gates of said memory cells of each of said plurality of NAND cells are respectively connected; address decoding means for receiving said first high voltage generated by said first high voltage generator and an address input and selectively supplying said first high voltage to said plurality of word lines in accordance with said address input; and bit-line voltage supplying means for supplying one of said second high voltage generated by said second high voltage generator and said source voltage to said bit line.

Claim 10

A semiconductor integrated circuit device comprising: booster means for boosting a power source voltage; voltage limiting means comprising one or more Zener diodes connected in series, the voltage limiting means having two ends, one of the two ends being connected to an output terminal of said booster means, for limiting an output voltage of said booster means to a given value; and voltage setting means, connected to the other of the two ends of said voltage limiting means, for arbitrarily adjusting a voltage at said other end of said voltage limiting means, wherein said voltage setting means comprises: voltage generating means for generating an arbitrary voltage having a value between said other end of said voltage limiting means and a reference voltage, said voltage generating means comprising a plurality of resistors inserted in series between said other end of said voltage limiting means and said reference voltage and a plurality of voltage selecting means for selecting voltages appearing at nodes between said series-connected resistors in accordance with a control signal, voltage comparing means for receiving said arbitrary voltage generated by said voltage generating means as one input, comparison-voltage generating means for generating a comparison voltage to be supplied as an other input of said voltage comparing means, and a MOS type switching element which has a current path inserted between said other end of said voltage limiting means and said reference voltage and whose gate is controlled by a comparison output of said voltage comparing means.

Claim 11

A semiconductor integrated circuit device comprising: booster means for boosting a power source voltage; voltage limiting means comprising one or more Zener diodes connected in series, the voltage limiting means having two ends, one of the two ends being connected to an output terminal of said booster means, for limiting an output voltage of said booster means to a given value; and voltage setting means, connected to the other of the two ends of said voltage limiting means, for arbitrarily adjusting a voltage at said other end of said voltage limiting means, wherein said voltage setting means comprises: voltage generating means for generating an arbitrary voltage having a value between said other end of said voltage limiting means and a reference voltage, said voltage generating means comprising a plurality of resistors inserted in series between said other end of said voltage limiting means and said reference voltage and a plurality of voltage selecting means for selecting voltages appearing at nodes between said series-connected resistors in accordance with a control signal, voltage comparing means for receiving said arbitrary voltage generated by said voltage generating means as one input, comparison-voltage generating means for generating a comparison voltage to be supplied as an other input of said voltage comparing means, and a MOS type switching element which has a current path inserted between said other end of said voltage limiting means and said reference voltage and whose gate is controlled by a comparison output of said voltage comparing means.

Claim 12

The semiconductor integrated circuit device according to claim 8, wherein a Zener breakdown voltage of said Zener diodes is set in a range from 4 V to 7 V.

Claim 13

The semiconductor integrated circuit device according to claim 8, wherein each of said plurality of voltage selecting means comprises a transfer gate.

Claim 14

A semiconductor integrated circuit device comprising: booster means for boosting a power source voltage; voltage limiting means comprising one or more Zener diodes connected in series, the voltage limiting means having two ends, one of which is connected to an output terminal of said booster means, for limiting an output voltage of said booster means to a given value; voltage setting means, connected to the other of the two ends of said voltage limiting means, for arbitrarily adjusting a voltage at said other end of said voltage limiting means; a plurality of NAND cells each having a plurality of series-connected MOSFETs each having a floating gate and a control gate; a plurality of word lines to which said control gates of said memory cells of each of said plurality of NAND cells are respectively connected; and address decoding means, connected to said output terminal of said booster means, for selectively supplying a voltage appearing on said output terminal of said booster means to said plurality of word lines in accordance with an address input, wherein said voltage setting means comprises: voltage generating means for generating an arbitrary voltage having a value between said other end of said voltage limiting means and a reference voltage, said voltage generating means comprising a plurality of resistors inserted in series between said other end of said voltage limiting means and said reference voltage and a plurality of voltage selecting means for selecting voltages appearing at nodes between said series-connected resistors in accordance with a control signal, voltage comparing means for receiving said arbitrary voltage generated by said voltage generating means as one input, comparison-voltage generating means for generating comparison voltage to be supplied as an other input of said voltage comparing means, and a MOS type switching element which has a current path inserted between said other end of said voltage limiting means and said reference voltage and whose gate is controlled by a comparison output of said voltage comparing means.

Claim 15

A semiconductor integrated circuit device comprising: booster means for boosting a power source voltage; voltage limiting means comprising one or more Zener diodes connected in series, the voltage limiting means having two ends, one of which is connected to an output terminal of said booster means, for limiting an output voltage of said booster means to a given value; voltage setting means, connected to the other of the two ends of said voltage limiting means, for arbitrarily adjusting a voltage at said other end of said voltage limiting means; a plurality of NAND cells each having a plurality of series-connected MOSFETs each having a floating gate and a control gate; a plurality of word lines to which said control gates of said memory cells of each of said plurality of NAND cells are respectively connected; and address decoding means, connected to said output terminal of said booster means, for selectively supplying a voltage appearing on said output terminal of said booster means to said plurality of word lines in accordance with an address input, wherein said voltage setting means comprises: voltage generating means for generating an arbitrary voltage having a value between said other end of said voltage limiting means and a reference voltage, said voltage generating means comprising a plurality of resistors inserted in series between said other end of said voltage limiting means and said reference voltage and a plurality of voltage selecting means for selecting voltages appearing at nodes between said series-connected resistors in accordance with a control signal, voltage comparing means for receiving said arbitrary voltage generated by said voltage generating means as one input, comparison-voltage generating means for generating comparison voltage to be supplied as an other input of said voltage comparing means, and a MOS type switching element which has a current path inserted between said other end of said voltage limiting means and said reference voltage and whose gate is controlled by a comparison output of said voltage comparing means.

Claim 16

The semiconductor integrated circuit device according to claim 11, wherein a Zener breakdown voltage of said Zener diodes is set in a range from 4 V to 7 V.

Claim 17

The semiconductor integrated circuit device according to claim 11, wherein each of said plurality of voltage selecting means comprises a transfer gate.

Claim 18

A semiconductor integrated circuit device comprising: booster means for boosting a power source voltage; voltage limiting means for limiting an output voltage of said booster means to a given value; and voltage detecting means for detecting said output voltage of said booster means, whereby a function of said booster means is controlled in accordance with an output of said voltage detecting means, wherein said booster means includes an oscillation circuit, controlled in accordance with a detection result of said voltage detecting means, whereby an oscillation period of said oscillation circuit changes in accordance with said detection result of said voltage detecting means.

Claim 19

A semiconductor integrated circuit device comprising: booster means for boosting a power source voltage; voltage limiting means for limiting an output voltage of said booster means to a given value; and voltage detecting means for detecting said output voltage of said booster means, whereby a function of said booster means is controlled in accordance with an output of said voltage detecting means, wherein said booster means includes an oscillation circuit, controlled in accordance with a detection result of said voltage detecting means, whereby an oscillation period of said oscillation circuit changes in accordance with said detection result of said voltage detecting means.

Claim 20

The semiconductor integrated circuit device according to claim 14, wherein said oscillation circuit is controlled so that said oscillation period becomes longer than before when said output voltage of said booster means exceeds a predetermined value.

Claim 21

The semiconductor integrated circuit device according to claim 14, wherein said booster means includes at least two oscillation circuits having different oscillation periods, and said function of said booster means is controlled in such a way that one of outputs of said at least two oscillation circuits is selected in accordance with said detection result of said voltage detecting means.

Claim 22

The semiconductor integrated circuit device according to claim 14, wherein said booster means includes first and second oscillation circuits having different oscillation periods, and said function of said booster means is controlled in such a way that an output of said first oscillation circuit is selected when said output voltage of said booster means is equal to or below a predetermined value and an output of said second oscillation circuit whose oscillation period is longer than that of said first oscillation circuit is selected when said output voltage of said booster means exceeds a predetermined value.