Nonvolatile semiconductor memory device for preventing erroneous operation caused by over-erase phenomenon

Claim 1

A nonvolatile semiconductor memory device comprising: a plurality of word lines; a plurality of bit lines; a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable; and a source power supply circuit, connected to sources of said nonvolatile memory cells, for applying one of a first voltage, a second voltage, and a third voltage to said sources of said nonvolatile memory cells, said first voltage being applied to negate an influence caused by an over-erase phenomenon at the time of a reading operation, said second voltage being used to write data to said memory cells, and said third voltage being used to erase data of said memory cells, said source power supply circuit comprising: a read bias voltage generation circuit for generating said first voltage; a write bias voltage generation circuit for generating said second voltage; an erase bias voltage generation circuit for generating said third voltage; and a power source switching circuit, said power source switching circuit being connected to said read bias voltage generation circuit, said write bias voltage generation circuit, and said erase bias voltage generation circuit for selecting said first voltage when reading data from said memory cells, said second voltage when writing data to said memory cells, and said third voltage when erasing data of said memory cells.