Process for manufacturing a multi-chip module

Claim 2

A process for manufacturing a multi-chip module, comprising the steps of: mounting on a substrate first and second semiconductor chips formed with a plurality of semiconductor elements on circuit forming surfaces and having different functions, and each of said first and second semiconductor chips having a mark; measuring the position of said marks of said first and second semiconductor chips to obtain measured data of said marks; transforming said measured data of said marks into positional coordinates in relation to said substrate to obtain transformed data of said marks; forming an insulating film over said circuit forming surfaces of said first and second semiconductor chips; forming first and second connection holes in said insulating film over said circuit forming surfaces of said first and second semiconductor chips using said transformed data of said marks of said first and second chips; and forming a wiring layer across said first and second connection holes to connect said first and second semiconductor chips electrically.

Claim 3

A process according to claim 1, wherein said first and second semiconductor chips are tested before said step of mounting on said substrate.

Claim 4

A process according to claim 2, wherein said first and second semiconductor chips have their circuit forming surfaces arranged therearound with scribe areas, in which testing pads are arranged.

Claim 5

A process according to claim 3, wherein the tests are accomplished in a wafer state.

Claim 6

A process according to claim 4, wherein said tests are accomplished in the wafer state before said first and second semiconductor chips are diced.

Claim 7

A process according to claim 2, wherein the tests are accomplished in a wafer state.

Claim 8

A process according to claim 2, wherein said wafer is arranged with testing circuits.

Claim 9

A process according to claim 1, wherein said first and second holes are formed by a direct laser or electron beam drawing method.

Claim 10

A process according to claim 1, wherein said first and second semiconductor chips are shaped square and said marks are positioned at the four corners of each of said first and second semiconductor chips.

Claim 11

A process according to claim 9, wherein said substrate is shaped square and marks are positioned at the four corners of said substrate.

Claim 12

A process for manufacturing a multi-chip module, comprising the steps of: mounting on a substrate at least one semiconductor chip formed with a plurality of semiconductor elements with marks formed on a circuit forming surface thereof; measuring the position of said marks relative to said substrate to obtain measured data of said marks; transforming said measured data of said marks into positional coordinates in relation to said substrate to obtain transformed data of said marks; forming an insulating film over said circuit forming surface of said semiconductor chip and said substrate; forming first and second connection holes in said insulating film over said circuit forming surface of said semiconductor chip and said substrate using said transformed data of said mark of said chip; and forming a wiring layer across said first and second connection holes to electrically connect said semiconductor chip and said substrate.

Claim 13

A process for manufacturing a multi-chip module, comprising the steps of: mounting on a substrate at least one semiconductor chip formed with a plurality of semiconductor elements with marks formed on a circuit forming surface thereof; measuring the position of said marks relative to said substrate to obtain measured data of said marks; transforming said measured data of said marks into positional coordinates in relation to said substrate to obtain transformed data of said marks; forming an insulating film over said circuit forming surface of said semiconductor chip and said substrate; forming first and second connection holes in said insulating film over said circuit forming surface of said semiconductor chip and said substrate using said transformed data of said mark of said chip; and forming a wiring layer across said first and second connection holes to electrically connect said semiconductor chip and said substrate.

Claim 14

A process according to claim 11, wherein said first and second holes are formed by a direct laser or electron beam drawing method.

Claim 15

A process according to claim 11, wherein said semiconductor chip is shaped square and said marks are positioned at the four corners of said semiconductor chip.

Claim 16

A process according to claim 12, wherein said substrate is shaped square and said marks are positioned at the four corners of said substrate.

Claim 17

A process for manufacturing a multi-chip module comprising the steps of: mounting on a substrate a first semiconductor chip having a plurality of semiconductor elements, first wirings and a first mark on a circuit forming surface thereof, and a second semiconductor chip having a plurality of semiconductor elements, second wirings and a second mark on a circuit forming surface thereof; measuring the position of said first and second marks of said first and second semiconductor chips to obtain measured data of said marks; transforming said measured data of said first and second marks into positional coordinates in relation to said substrate to obtain transformed data of said marks; forming a conductive film over said first and second wirings of said first and second semiconductor chips; forming third wirings from said conductive film, each connecting one of said first wiring and one of said second wirings over said circuit forming surfaces of said first and second semiconductor chips using said transformed data of said marks of said first and second chips.

Claim 18

A process for manufacturing a multi-chip module comprising the steps of: mounting on a substrate a first semiconductor chip having a plurality of semiconductor elements, first wirings and a first mark on a circuit forming surface thereof, and a second semiconductor chip having a plurality of semiconductor elements, second wirings and a second mark on a circuit forming surface thereof; measuring the position of said first and second marks of said first and second semiconductor chips to obtain measured data of said marks; transforming said measured data of said first and second marks into positional coordinates in relation to said substrate to obtain transformed data of said marks; forming a conductive film over said first and second wirings of said first and second semiconductor chips; forming third wirings from said conductive film, each connecting one of said first wiring and one of said second wirings over said circuit forming surfaces of said first and second semiconductor chips using said transformed data of said marks of said first and second chips.

Claim 19

A process according to claim 15, wherein said third wirings are formed by a direct electron beam drawing method.

Claim 20

A process according to claim 16, wherein said first and second chips are shaped square and said first and second marks are positioned at four corners of each of said first and second semiconductor chips.

Claim 21

A process according to claim 16, wherein said first and second semiconductor chips are tested before said step of mounting on said substrate.

Claim 22

A process according to claim 18, wherein each of said first and second semiconductor chips is tested in a wafer state.

Claim 23

A process according to claim 19, wherein each of said first and second semiconductor chips is tested before said first and second semiconductor chips are diced.

Claim 24

A process according to claim 16, wherein each of said first and second semiconductor chips has said circuit forming surface arranged therearound with scribe area, in which testing pads are arranged.

Claim 25

A process according to claim 15, wherein said third wirings are formed by a direct laser beam drawing method.