Patent US5386552A successfully refreshed from Google Patents.
US5386552A
Expired / Lapsed
US
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Preservation of a computer system processing state in a mass storage device
Assignee: Intel Corp
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Filing: 1994-07-18
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Granted: 1995-01-31
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Expires: 2014-07-18
Abstract
Abstract A computer system wherein the processing state of the system may be saved and restored on a mass storage device upon the occurrence of a triggering event. The computer system of the present invention comprises a processor and various memory areas and system resources. Main memory includes several areas including a system management area comprising a segment of isolated random access memory within main memory. The system management area may only be accessed while the processor is in a system management interrupt state. The remaining portions of main memory are freely accessible (i.e. non-isolated) by any interrupt or noninterrupt processing logic. The basic approach of the present invention for saving the processing state of a computer system in nonvolatile storage is to: (1) sense a save system state triggering event; (2) write the contents of system registers and memory to a nonvolatile mass storage device; and (3) enter a suspend state and wait for a resume triggering event or power off the computer system completely. The basic approach of the present invention for restoring the processing state of the computer system from nonvolatile memory is to: (1) sense the resumption of processing of the application of power to the computer system; (2) read the contents of a previously save processing state from a nonvolatile mass storage device and restore the contents of memory and computer system registers; and (3) return control to the previously running application program.
Inventors
- 👤 John I. Garney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:20
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/461; G06F9/44; G06F9/4401; G06F9/4418
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
266 words
In a computer system for operating in a protected and a nonprotected mode having a processor, a memory, and a nonvolatile mass storage device, said nonprotected mode including a system management interrupt mode, said memory being partitioned into an isolated memory and a non-isolated memory, said isolated memory being only accessible from said system management interrupt mode, said non-isolated memory being partitioned into a first portion of non-isolated memory that can only be accessed when said processor is operating in said protected mode and a second portion of non-isolated memory that can be accessed when said processor is operating in either said protected or nonprotected mode, a process for saving the processing state of said computer system, said process comprising the steps of: interrupting the execution of said processor upon the occurrence of a triggering event, said triggering event forcing said processor to operate in said system management interrupt mode; activating a first save system state module, said first save system state module operating in said system management interrupt mode, said first save system state module having access to said isolated memory and said second portion of non-isolated memory, said first save system state module writing information from said isolated memory into said second portion Of non-isolated memory; and activating a second save system state module, said second save system state module operating in said protected mode, said second save system state module having access to said first and second portion of non-isolated memory, said second save system state module writing information from said non-isolated memory to a predetermined location on said nonvolatile mass storage device.
Claim 2
Dependent Claim
266 words
In a computer system for operating in a protected and a nonprotected mode having a processor, a memory, and a nonvolatile mass storage device, said nonprotected mode including a system management interrupt mode, said memory being partitioned into an isolated memory and a non-isolated memory, said isolated memory being only accessible from said system management interrupt mode, said non-isolated memory being partitioned into a first portion of non-isolated memory that can only be accessed when said processor is operating in said protected mode and a second portion of non-isolated memory that can be accessed when said processor is operating in either said protected or nonprotected mode, a process for saving the processing state of said computer system, said process comprising the steps of: interrupting the execution of said processor upon the occurrence of a triggering event, said triggering event forcing said processor to operate in said system management interrupt mode; activating a first save system state module, said first save system state module operating in said system management interrupt mode, said first save system state module having access to said isolated memory and said second portion of non-isolated memory, said first save system state module writing information from said isolated memory into said second portion Of non-isolated memory; and activating a second save system state module, said second save system state module operating in said protected mode, said second save system state module having access to said first and second portion of non-isolated memory, said second save system state module writing information from said non-isolated memory to a predetermined location on said nonvolatile mass storage device.
Claim 3
Dependent Claim
33 words
The process as claimed in claim 1 further including the step of: transferring control from said first save system state module to said second save system state module by modifying processor state information.
Claim 4
Dependent Claim
32 words
The process as claimed in claim 1 further including the step of: transferring control from said second save system state module to said first save system state module by generating an interrupt.
Claim 5
Dependent Claim
17 words
The process as claimed in claim 1 further including the step of: entering a low power mode.
Claim 6
Dependent Claim
29 words
The process as claimed in claim 1 further including the step of: automatically powering off said computer system from a low power mode after a time-out period has elapsed.
Claim 7
Dependent Claim
247 words
In a computer system for operating in a protected and a nonprotected mode having a processor, a memory, and a nonvolatile mass storage device, said nonprotected mode including a system management interrupt mode, said memory being partitioned into an isolated memory and a non-isolated memory, said isolated memory being only accessible from said system management interrupt mode said non-isolated memory being partitioned into a first portion of non-isolated memory that can only be accessed when said processor is operating in said protected mode and a second portion of non-isolated memory that can be accessed when said processor is operating in either said protected or nonprotected mode, a process for restoring the processing state of said computer system, said process comprising the steps of: resetting said processor; activating a first restore system state module, said first restore system state module operating in said system management interrupt mode, said first restore system state module having access to said isolated memory and said second portion of non-isolated memory, said first restore system state module writing information from said second portion of non-isolated memory into said isolated memory; and activating a second restore system state module, said second restore system state module operating in said protected mode, said second restore system state module having access to said first and second portion of non-isolated memory, said second restore system state module writing information from a predetermined location on said nonvolatile mass storage device to said first and second portion of non-isolated memory.
Claim 8
Dependent Claim
247 words
In a computer system for operating in a protected and a nonprotected mode having a processor, a memory, and a nonvolatile mass storage device, said nonprotected mode including a system management interrupt mode, said memory being partitioned into an isolated memory and a non-isolated memory, said isolated memory being only accessible from said system management interrupt mode said non-isolated memory being partitioned into a first portion of non-isolated memory that can only be accessed when said processor is operating in said protected mode and a second portion of non-isolated memory that can be accessed when said processor is operating in either said protected or nonprotected mode, a process for restoring the processing state of said computer system, said process comprising the steps of: resetting said processor; activating a first restore system state module, said first restore system state module operating in said system management interrupt mode, said first restore system state module having access to said isolated memory and said second portion of non-isolated memory, said first restore system state module writing information from said second portion of non-isolated memory into said isolated memory; and activating a second restore system state module, said second restore system state module operating in said protected mode, said second restore system state module having access to said first and second portion of non-isolated memory, said second restore system state module writing information from a predetermined location on said nonvolatile mass storage device to said first and second portion of non-isolated memory.
Claim 9
Dependent Claim
33 words
The process as claimed in claim 6 further including the step of: transferring control from said first restore system state module to said second restore system state module by modifying processor state information.
Claim 10
Dependent Claim
32 words
The process as claimed in claim 6 further including the step of: transferring control from said second restore system state module to said first restore system state module by generating an interrupt.
Claim 11
Dependent Claim
20 words
The process as claimed in claim 6 further including the step of: returning processing control to a previously executing program.
Claim 12
Dependent Claim
44 words
The process as claimed in claim 6 further including a step of resuming operation of said computer system from a low power mode, said step of resuming being performed without reading a complete saved system state image stored on said nonvolatile mass storage device.
Claim 13
Dependent Claim
25 words
The process as claimed in claim 6 further including the steps of: determining if the contents of a battery backed random access memory is valid.
Claim 14
Dependent Claim
222 words
In a computer system for operating in a protected and nonprotected mode having a processor, a memory, and a nonvolatile mass storage device, said nonprotected mode including a system management interrupt mode, said memory being partitioned into an isolated memory and a non-isolated memory, said isolated memory being only accessible from said system management interrupt mode, said non-isolated memory being accessible when said processor is operating in either said protected or nonprotected mode, a process for saving the processing state of said computer system, said process comprising the steps of: interrupting the execution of said processor upon the occurrence of a triggering event, said triggering event forcing said processor to operate in said system management interrupt mode; activating a first save system state module, said first save system state module operating in said system management interrupt mode, said first save system state module having access to said isolated memory and said non-isolated memory, said first save system state module writing information from said isolated memory into said non-isolated memory; and activating a second save system state module, said second save system state module operating in said nonprotected mode, said second save system state module having access to said non-isolated memory, said second save system state module writing information from said non-isolated memory to a predetermined location on said nonvolatile mass storage device.
Claim 15
Dependent Claim
222 words
In a computer system for operating in a protected and nonprotected mode having a processor, a memory, and a nonvolatile mass storage device, said nonprotected mode including a system management interrupt mode, said memory being partitioned into an isolated memory and a non-isolated memory, said isolated memory being only accessible from said system management interrupt mode, said non-isolated memory being accessible when said processor is operating in either said protected or nonprotected mode, a process for saving the processing state of said computer system, said process comprising the steps of: interrupting the execution of said processor upon the occurrence of a triggering event, said triggering event forcing said processor to operate in said system management interrupt mode; activating a first save system state module, said first save system state module operating in said system management interrupt mode, said first save system state module having access to said isolated memory and said non-isolated memory, said first save system state module writing information from said isolated memory into said non-isolated memory; and activating a second save system state module, said second save system state module operating in said nonprotected mode, said second save system state module having access to said non-isolated memory, said second save system state module writing information from said non-isolated memory to a predetermined location on said nonvolatile mass storage device.
Claim 16
Dependent Claim
33 words
The process as claimed in claim 12 further including the step of: transferring control from said first save system state module to said second save system state module by modifying processor state information.
Claim 17
Dependent Claim
32 words
The process as claimed in claim 12 further including the step of: transferring control from said second save system state module to said first save system state module by generating an interrupt.
Claim 18
Dependent Claim
17 words
The process as claimed in claim 12 further including the step of: entering a low power mode.
Claim 19
Dependent Claim
29 words
The process as claimed in claim 12 further including the step of: automatically powering off said computer system from a low power mode after a time-out period has elapsed.
Claim 20
Dependent Claim
182 words
In a computer system for operating in a protected and a nonprotected mode having a processor, a memory, and a nonvolatile mass storage device, said nonprotected mode including a system management interrupt mode, said memory being partitioned into an isolated memory and a non-isolated memory, said isolated memory being only accessible from said system management interrupt mode, a process for restoring the processing state of said computer system, said process comprising the steps of: resetting said processor; activating a first restore system state module, said first restore system state module operating in said system management interrupt mode, said first restore system state module having access to said isolated memory and said non-isolated memory, said first restore system state module writing information from said non-isolated memory into said isolated memory; and activating a second restore system state module, said second restore system state module operating in said nonprotected mode, said second restore system state module having access to said non-isolated memory, said second restore system state module writing information from a predetermined location on said nonvolatile mass storage device to said non-isolated memory.
Claim 21
Dependent Claim
182 words
In a computer system for operating in a protected and a nonprotected mode having a processor, a memory, and a nonvolatile mass storage device, said nonprotected mode including a system management interrupt mode, said memory being partitioned into an isolated memory and a non-isolated memory, said isolated memory being only accessible from said system management interrupt mode, a process for restoring the processing state of said computer system, said process comprising the steps of: resetting said processor; activating a first restore system state module, said first restore system state module operating in said system management interrupt mode, said first restore system state module having access to said isolated memory and said non-isolated memory, said first restore system state module writing information from said non-isolated memory into said isolated memory; and activating a second restore system state module, said second restore system state module operating in said nonprotected mode, said second restore system state module having access to said non-isolated memory, said second restore system state module writing information from a predetermined location on said nonvolatile mass storage device to said non-isolated memory.
Claim 22
Dependent Claim
25 words
The process as claimed in claim 17 further including the steps of: determining if the contents of a battery backed random access memory is valid.
Claim 23
Dependent Claim
33 words
The process as claimed in claim 17 further including the step of: transferring control from said first restore system state module to said second restore system state module by modifying processor state information.
Claim 24
Dependent Claim
32 words
The process as claimed in claim 17 further including the step of: transferring control from said second restore system state module to said first restore system state module by generating an interrupt.
Claim 25
Dependent Claim
20 words
The process as claimed in claim 17 further including the step of: returning processing control to a previously executing program.
Claim 26
Dependent Claim
44 words
The process as claimed in claim 17 further including a step of resuming operation of said computer system from a low power mode, said step of resuming being performed without reading a complete saved system state image stored on said nonvolatile mass storage device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-30 | 1998-08-01 | 1999-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-30 | 2002-08-01 | 2003-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-30 | 2006-08-01 | 2007-01-31 | $7700.00 | Window Closed / Lapsed |