Patent US5386511A successfully refreshed from Google Patents.
US5386511A
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Multiprocessor system and data transmission apparatus thereof
Assignee: International Business Machines Corp
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Filing: 1992-04-17
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Granted: 1995-01-31
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Expires: 2012-04-17
Abstract
Abstract The bandwidth of the data transfer among a main memory and snoopy caches is improved by solving the bus bottleneck in a multiprocessor system using a snoopy cache technique. Shared bus coupling is employed for an address/command bus requiring bus snoop whereas multiple data paths coupled by an interconnection network are used for the data bus not requiring bus snoop. The multiple data paths reflect the order of the snoopy operations on the order of data transfer such as to maintain data consistency among the caches.
Inventors
- 👤 Hiroki Murata
- 👤 Shigenori Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:27
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0813
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
104 words
A multiprocessor system comprising: a plurality of processors; a main memory comprising a plurality of sections; a plurality of cache memories provided for said processors; interconnection network means for selectively connecting said cache memories to said sections for the transfer of data therebetween in accordance with address information for said data; shared bus means coupled to said cache memories for transferring said address information to said cache memories; and control means provided for said cache memories for monitoring said address information transferred through said shared bus means to ensure consistency of data stored in said cache memories with data stored in said main memory.
Claim 2
Dependent Claim
104 words
A multiprocessor system comprising: a plurality of processors; a main memory comprising a plurality of sections; a plurality of cache memories provided for said processors; interconnection network means for selectively connecting said cache memories to said sections for the transfer of data therebetween in accordance with address information for said data; shared bus means coupled to said cache memories for transferring said address information to said cache memories; and control means provided for said cache memories for monitoring said address information transferred through said shared bus means to ensure consistency of data stored in said cache memories with data stored in said main memory.
Claim 3
Dependent Claim
48 words
The multiprocessor system according to claim 1 wherein said address information contains a portion identifying the section of said main memory that is being accessed for data transfer, said interconnection means connecting one of said cache memories to the section identified by said portion of said address information.
Claim 4
Dependent Claim
49 words
The multiprocessor system according to claim 1 wherein said cache memories store units of data comprising segments, said main memory being organized into said sections in such a manner that the segments of a unit of data stored in one of said cache memories are distributed among said sections.
Claim 5
Dependent Claim
40 words
The multiprocessor system according to claim 1 wherein data transfer between said cache memories is performed by data transfer from a source cache memory to said main memory and data transfer from said main memory to a destination cache memory.
Claim 6
Dependent Claim
109 words
A multiprocessor system comprising: a plurality of processors; a main memory comprising a plurality of sections; a plurality of cache memories provided for said processors; interconnection network means for selectively connecting said cache memories to said sections and to said cache memories for the transfer of data therebetween in accordance with address information for said data; shared bus means coupled to said cache memories for transferring said address information to said cache memories; and control means provided for said cache memories for monitoring said address information transferred through said shared bus means to ensure consistency of data stored in said cache memories with data stored in said main memory.
Claim 7
Dependent Claim
109 words
A multiprocessor system comprising: a plurality of processors; a main memory comprising a plurality of sections; a plurality of cache memories provided for said processors; interconnection network means for selectively connecting said cache memories to said sections and to said cache memories for the transfer of data therebetween in accordance with address information for said data; shared bus means coupled to said cache memories for transferring said address information to said cache memories; and control means provided for said cache memories for monitoring said address information transferred through said shared bus means to ensure consistency of data stored in said cache memories with data stored in said main memory.
Claim 8
Dependent Claim
79 words
A data transmission apparatus used in a multiprocessor system having a plurality of processors, cache memories provided for said processors, and a main memory which comprises a plurality of sections, comprising: interconnection network means for selectively connecting said cache memories to said sections of said main memory for the transfer of data therebetween in accordance with address information for said data; and shared bus means coupled to said cache memories for transferring said address information to said cache memories.
Claim 9
Dependent Claim
79 words
A data transmission apparatus used in a multiprocessor system having a plurality of processors, cache memories provided for said processors, and a main memory which comprises a plurality of sections, comprising: interconnection network means for selectively connecting said cache memories to said sections of said main memory for the transfer of data therebetween in accordance with address information for said data; and shared bus means coupled to said cache memories for transferring said address information to said cache memories.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-30 | 1998-08-01 | 1999-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-30 | 2002-08-01 | 2003-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-30 | 2006-08-01 | 2007-01-31 | $7700.00 | Window Closed / Lapsed |