Reference voltage generator

Claim 2

A reference voltage generator comprising: a constant voltage generator coupled between a first operation potential and a second operation potential; and a voltage sampling means for sampling an output voltage of said constant voltage generator; wherein said constant voltage generator includes: first and second MOS transistors; and a first switching means coupled between said first operation potential and said second operation potential so as to be connected in series to respective source-drain paths of said first and second MOS transistors; wherein said constant voltage generator serves to output, at a first output terminal, a first voltage proportional to a difference between threshold voltages of said first and second MOS transistors; wherein said voltage sampling means includes: a second switching means having one end coupled with said first output terminal of said constant voltage generator; and a first capacitor connected to the other end of said second switching means to thereby store said first voltage of said constant voltage generator; and wherein after said first capacitor of said voltage sampling means is charged with said first voltage of said constant voltage generator, said second switching means of said voltage sampling means is turned off and then said first switching means of said constant voltage generator is turned off to thereby reduce a current consumed by said constant voltage generator.

Claim 3

A reference voltage generator according to claim 1, wherein said first switching means of said constant voltage generator is turned on periodically, and wherein said second switching means of said voltage sampling means is turned on when said first switching means of said constant voltage generator is on, so that said first capacitor of said voltage sampling means restores said first voltage of said constant voltage generator.

Claim 4

A reference voltage generator according to claim 2, wherein said voltage sampling means further includes an output means for outputting the voltage held by said first capacitor, and wherein said output means includes a third MOS transistor having a gate and a source so that said first capacitor of said voltage sampling means is connected between said gate and said source.

Claim 5

A reference voltage generator according to claim 1, wherein said constant voltage generator serves to output, at a second output terminal, a second voltage proportional to a difference between threshold voltages of said first and second MOS transistors, and wherein said first voltage and said second voltage are voltages based on said first operation potential.

Claim 6

A reference voltage generator according to claim 4, wherein said voltage sampling means further includes: a third switching means having one end coupled with said second output terminal of said constant voltage generator; a second capacitor for storing said second voltage of said constant voltage generator through said third switching means; a voltage converting means for converting said first voltage stored in said first capacitor into a third voltage based on said second operation potential; and means for outputting a larger one of said second voltage stored in said second capacitor and said third voltage by reference to said second potential.

Claim 7

A reference voltage generator according to claim 5, wherein said first switching means of said constant voltage generator is turned on periodically, and wherein said second and third switching means of said voltage sampling means are turned on when said first switching means of said constant voltage generator is on, so that said first and second capacitors of said voltage sampling means restore said first and second voltages of said constant voltage generator respectively.

Claim 8

Dynamic random access memory comprising: a first terminal supplied with a first operation potential; a second terminal supplied with a second operation potential; a plurality of word lines; a plurality of data lines disposed so as to intersect said plurality of word lines; a plurality of memory cells disposed at desired intersections of said plurality of word lines and said plurality of data lines; a decoder for selecting one word line from said plurality of word lines; a word line voltage generator supplied with said first and second operation potentials to thereby generate a third operation potential; a word line driver for connecting said third operation potential and said one word line selected from said plurality of word line by said decoder; a reference voltage generator supplied with said first and second operation potentials to thereby generate a reference voltage; a subtraction circuit for converting the level of a voltage supplied to a word line into a value obtained by subtracting said first operation potential from said voltage supplied to said word line; and a comparator for comparing an output voltage of said subtraction circuit and said reference voltage; wherein said comparator serves to control said word line voltage generator so that said output voltage of said subtraction circuit and said reference voltage are made substantially equal to each other; wherein each of said plurality of memory cells includes an MOS transistor having its gate connected to a corresponding one of said plurality of word lines, and a first capacitor having its one end connected to a source or drain of said MOS transistor; wherein said reference voltage generator includes: a constant voltage generator coupled between said first operation potential and said second operation potential; and a voltage sampling means for sampling an output voltage of said constant voltage generator; wherein said constant voltage generator includes: first and second MOS transistors; and a first switching means coupled between said first operation potential and said second operation potential so as to be connected in series to respective source-drain paths of said first and second MOS transistors; wherein said constant voltage generator serves to output, at a first output terminal, a first voltage proportional to a difference between threshold voltages of said first and second MOS transistors; wherein said voltage sampling means includes: a second switching means having one end coupled with said first output terminal of said constant voltage generator; and a first capacitor connected to the other end of said second switching means to thereby store said first voltage of said constant voltage generator; and wherein after said first capacitor of said voltage sampling means is charged with said first voltage of said constant voltage generator, said second switching means of said voltage sampling means is turned off and then said first switching means of said constant voltage generator is turned off to thereby reduce a current consumed by said constant voltage generator.

Claim 9

Dynamic random access memory comprising: a first terminal supplied with a first operation potential; a second terminal supplied with a second operation potential; a plurality of word lines; a plurality of data lines disposed so as to intersect said plurality of word lines; a plurality of memory cells disposed at desired intersections of said plurality of word lines and said plurality of data lines; a decoder for selecting one word line from said plurality of word lines; a word line voltage generator supplied with said first and second operation potentials to thereby generate a third operation potential; a word line driver for connecting said third operation potential and said one word line selected from said plurality of word line by said decoder; a reference voltage generator supplied with said first and second operation potentials to thereby generate a reference voltage; a subtraction circuit for converting the level of a voltage supplied to a word line into a value obtained by subtracting said first operation potential from said voltage supplied to said word line; and a comparator for comparing an output voltage of said subtraction circuit and said reference voltage; wherein said comparator serves to control said word line voltage generator so that said output voltage of said subtraction circuit and said reference voltage are made substantially equal to each other; wherein each of said plurality of memory cells includes an MOS transistor having its gate connected to a corresponding one of said plurality of word lines, and a first capacitor having its one end connected to a source or drain of said MOS transistor; wherein said reference voltage generator includes: a constant voltage generator coupled between said first operation potential and said second operation potential; and a voltage sampling means for sampling an output voltage of said constant voltage generator; wherein said constant voltage generator includes: first and second MOS transistors; and a first switching means coupled between said first operation potential and said second operation potential so as to be connected in series to respective source-drain paths of said first and second MOS transistors; wherein said constant voltage generator serves to output, at a first output terminal, a first voltage proportional to a difference between threshold voltages of said first and second MOS transistors; wherein said voltage sampling means includes: a second switching means having one end coupled with said first output terminal of said constant voltage generator; and a first capacitor connected to the other end of said second switching means to thereby store said first voltage of said constant voltage generator; and wherein after said first capacitor of said voltage sampling means is charged with said first voltage of said constant voltage generator, said second switching means of said voltage sampling means is turned off and then said first switching means of said constant voltage generator is turned off to thereby reduce a current consumed by said constant voltage generator.

Claim 10

Dynamic random access memory according to claim 7, wherein said first switching means of said constant voltage generator is turned on periodically, and wherein said second switching means of said voltage sampling means is turned on when said first switching means of said constant voltage generator is on, so that said first capacitor of said voltage sampling means restores said first voltage of said constant voltage generator.

Claim 11

Dynamic random access memory according to claim 8, wherein said voltage sampling means further includes means to output a voltage held by said first capacitor, and wherein said output means includes a third MOS transistor in which said first capacitor of said voltage sampling means is connected between its gate and its source.

Claim 12

Dynamic random access memory according to claim 7, wherein said constant voltage generator serves to output, at a second output terminal, a second voltage proportional to a difference between threshold voltages of said first and second MOS transistors, and wherein said first voltage and said second voltage are voltages based on said first operation potential.

Claim 13

Dynamic random access memory according to claim 10, wherein said voltage sampling means further includes: a third switching means having one end coupled with said second output terminal of said constant voltage generator; a second capacitor for storing said second voltage of said constant voltage generator through said third switching means; a voltage converting means for converting said first voltage stored in said first capacitor into a third voltage based on said second operation potential; and means for outputting a larger one of said second voltage stored in said second capacitor and said third voltage by reference to said second potential.

Claim 14

Dynamic random access memory according to claim 11, wherein said first switching means of said constant voltage generator is turned on periodically, and wherein said second and third switching means of said voltage sampling means are turned on when said first switching means of said constant voltage generator is on, so that said first and second capacitors of said voltage sampling means restore said first and second voltages of said constant voltage generator respectively.

Claim 15

Dynamic random access memory according to claim 7, wherein said first voltage of said constant voltage generator is set to a value substantially equal to threshold voltages of MOS transistors in said plurality of memory cells.