US5384581A
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Image processing apparatus
Assignee: Canon Inc
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Filing: 1993-05-25
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Granted: 1995-01-24
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Expires: 2013-05-25
Abstract
Abstract There is disclosed a control circuit of a memory device of a random access type for storing first data and second data whose reading/writing cycle time is longer than that of the first data, including: a memory circuit for reading/writing a predetermined number of first data into/from each memory block which is obtained by dividing the memory device into at least two or more memory blocks, for reading/writing the second data into/from the other memory blocks, and for supplying address signals for the reading/writing cycle period of time of the second data; and a memory switching circuit for switching and using the memory blocks in order to read/write the first and second data, so that the memory device can be accessed at a high speed by using a small capacity.
Inventors
- 👤 Ikumasa Ikeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:53
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/907; H04N9/00; H04N9/64
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
114 words
An image processing apparatus comprising: a plurality of memory blocks; and control means for making said plurality of memory blocks store first data and second data, an access cycle time of the second data being longer than an access cycle time of the first data, wherein said control means accesses a memory block for the second data in a period during which another memory block is accessed for the first data, and sets a row address of the memory block accessed for the first data during a quiescent period of access of the second data, the quiescent period being caused by a difference in the access cycle times of the first and second data.
Claim 2
Dependent Claim
114 words
An image processing apparatus comprising: a plurality of memory blocks; and control means for making said plurality of memory blocks store first data and second data, an access cycle time of the second data being longer than an access cycle time of the first data, wherein said control means accesses a memory block for the second data in a period during which another memory block is accessed for the first data, and sets a row address of the memory block accessed for the first data during a quiescent period of access of the second data, the quiescent period being caused by a difference in the access cycle times of the first and second data.
Claim 3
Dependent Claim
21 words
An apparatus according to claim 1, wherein each of said plurality of memory blocks is a dynamic random access memory (RAM).
Claim 4
Dependent Claim
24 words
An apparatus according to claim 1, wherein an access cycle of the second data is two times an access cycle of the first data.
Claim 5
Dependent Claim
21 words
An apparatus according to claim 1, wherein the first data is luminance data and the second data is color difference data.
Claim 6
Dependent Claim
18 words
An apparatus according to claim 1, wherein each of said plurality of memory blocks has a 1M-bit capacity.
Claim 7
Dependent Claim
17 words
An apparatus according to claim 1, further comprising supply means for supplying the first and second data.
Claim 8
Dependent Claim
30 words
An apparatus according to claim 6, wherein said supply means includes a first analog-to-digital (A/D) converter for the first data and a second analog-to-digital (A/D) converter for the second data.
Claim 9
Dependent Claim
24 words
An apparatus according to claim 7, wherein a clock for said first A/D converter is two times a clock for said second A/D converter.
Claim 10
Dependent Claim
113 words
An image processing apparatus comprising: generation means for generating luminance data and color data, a sampling number of the color data being fewer than a sampling number of the luminance data; a plurality of memory blocks; and memory control means for accessing, in said plurality of memory blocks, a memory block for the color data in a period during which another memory block is accessed for the luminance data, and for setting a row address of the memory block accessed for the luminance data during a quiescent period of access of the color data, the quiescent period being caused by a difference in the access cycle times of the luminance and color data.
Claim 11
Dependent Claim
113 words
An image processing apparatus comprising: generation means for generating luminance data and color data, a sampling number of the color data being fewer than a sampling number of the luminance data; a plurality of memory blocks; and memory control means for accessing, in said plurality of memory blocks, a memory block for the color data in a period during which another memory block is accessed for the luminance data, and for setting a row address of the memory block accessed for the luminance data during a quiescent period of access of the color data, the quiescent period being caused by a difference in the access cycle times of the luminance and color data.
Claim 12
Dependent Claim
15 words
An apparatus according to claim 9, wherein said generation means includes an analog-to-digital (A/D) converter.
Claim 13
Dependent Claim
21 words
An apparatus according to claim 9, wherein each of said plurality of memory blocks is a dynamic random access memory (RAM).
Claim 14
Dependent Claim
24 words
An apparatus according to claim 9, wherein a sampling number of the luminance data is two times a sampling number of the color data.
Claim 15
Dependent Claim
18 words
An apparatus according to claim 9, wherein each of said plurality of memory blocks has a 1M-bit capacity.
Claim 16
Dependent Claim
24 words
An apparatus according to claim 10, further comprising read means for reading the luminance data and the color data written into said memory block.
Claim 17
Dependent Claim
142 words
An image processing apparatus which comprises a memory device of random access type for storing first data and second data, a read/write cycle time of the second data being longer than a read/write cycle time of the first data, said apparatus comprising: first memory control means for reading/writing a predetermined number of first data from/into each of a plurality of memory blocks which form said memory device, reading/writing the second data from/into a memory block, and supplying a row address signal of the memory block accessed for the first data during a quiescent period of access of the second data, the quiescent period being caused by a difference in the read/write cycle times of the first and second data; and second memory control means for controlling said memory blocks to read/write the first and second data by selectively switching between memory blocks.
Claim 18
Dependent Claim
142 words
An image processing apparatus which comprises a memory device of random access type for storing first data and second data, a read/write cycle time of the second data being longer than a read/write cycle time of the first data, said apparatus comprising: first memory control means for reading/writing a predetermined number of first data from/into each of a plurality of memory blocks which form said memory device, reading/writing the second data from/into a memory block, and supplying a row address signal of the memory block accessed for the first data during a quiescent period of access of the second data, the quiescent period being caused by a difference in the read/write cycle times of the first and second data; and second memory control means for controlling said memory blocks to read/write the first and second data by selectively switching between memory blocks.
Claim 19
Dependent Claim
21 words
An apparatus according to claim 15, wherein the first data is luminance data and the second data is color difference data.
Claim 20
Dependent Claim
24 words
An apparatus according to claim 15, wherein an access cycle of the second data is two times an access cycle of the first data.
Claim 21
Dependent Claim
21 words
An apparatus according to claim 15, wherein each of said plurality of memory blocks is a dynamic random access memory (RAM).
Claim 22
Dependent Claim
29 words
An apparatus according to claim 1, wherein each of the memory blocks are alternately used for reading or writing the first and second data every predetermined period of time.
Claim 23
Dependent Claim
26 words
An apparatus according to claim 9, wherein each of the memory blocks are alternately accessed for the color and luminance data every predetermined period of time.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-23 | 1998-07-25 | 1999-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-23 | 2002-07-25 | 2003-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-23 | 2006-07-25 | 2007-01-24 | $7700.00 | Window Closed / Lapsed |