Patent US5384548A successfully refreshed from Google Patents.
US5384548A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Constant transconductance bias circuit and method
Assignee: The Ohio State University
•
Filing: 1993-08-25
•
Granted: 1995-01-24
•
Expires: 2013-08-25
Abstract
Abstract The reduction of the power supply voltage of VLSI circuits to 3.3 volts results in a significant loss in input and output swing in traditional CMOS analog circuits. In order to achieve rail-to-rail operation, n-channel and p-channel MOSFETs are placed in parallel so that at least one type of transistors are operating in a high gain region throughout the entire input range. However, circuit characteristics change as transistors turn on and off. A constant transconductance bias means enables the rail-to-rail CMOS differential stage to possess a constant transconductance over the entire common mode voltage range. Significantly, the bias circuit does not require any matching between the transistors of opposite types.
Inventors
- 👤 Satoshi Sakurai
- 👤 Mohammed Ismail
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 19:40
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/34; H03F3/343; H03F3/345; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F3/4521; H03F3/45479; H03F3/45632; H03F3/45695; H03F3/45699; H03F3/45708; H03F2200/00; H03F2200/162; H03F2203/00; H03F2203/45; H03F2203/45508
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
99 words
An integrated circuit comprising: a differential stage having a first differential pair of Field Effect Transistors (FETs) of a first conductivity type with a first bias current flowing therethrough and a second pair of differential FETs of a second conductivity type, electrically connected in parallel with the first pair of FETs, with a second bias current flowing therethrough; and constant transconductance bias means, electrically connected to said differential stage, for monitoring one of the first and second bias currents and dynamically controlling the other of the first and second bias currents to maintain constant transconductance of said differential stage.
Claim 2
Dependent Claim
99 words
An integrated circuit comprising: a differential stage having a first differential pair of Field Effect Transistors (FETs) of a first conductivity type with a first bias current flowing therethrough and a second pair of differential FETs of a second conductivity type, electrically connected in parallel with the first pair of FETs, with a second bias current flowing therethrough; and constant transconductance bias means, electrically connected to said differential stage, for monitoring one of the first and second bias currents and dynamically controlling the other of the first and second bias currents to maintain constant transconductance of said differential stage.
Claim 3
Dependent Claim
36 words
An integrated circuit according to claim 1 wherein the monitored one of said first and second bias currents is a common mode voltage-dependent current and wherein the associated differential pair of FETs are of p-type conductivity.
Claim 4
Dependent Claim
39 words
An integrated circuit according to claim 2 wherein the dynamically controlled one of said first and second bias currents is supplied by said constant transconductance bias means and wherein the associated differential pair of FETs are of n-type conductivity.
Claim 5
Dependent Claim
36 words
An integrated circuit according to claim 1 wherein the monitored one of said first and second bias currents is a common mode voltage-dependent current and wherein the associated differential pair of FETs are of n-type conductivity.
Claim 6
Dependent Claim
39 words
An integrated circuit according to claim 4 wherein the dynamically controlled one of the first and second bias currents is supplied by said constant transconductance bias means and wherein the associated differential pair of FETs are of p-type conductivity.
Claim 7
Dependent Claim
43 words
An integrated circuit according to claim 1 further comprising a first current source, electrically coupled to the constant transconductance bias means, for limiting said dynamically controlled bias current when the FETs through which the monitored bias current flows are operating in weak inversion.
Claim 8
Dependent Claim
43 words
An integrated circuit according to claim 6 further comprising a second current source, electrically coupled to the constant transconductance bias means, for limiting said monitored bias current when the FETs through which the dynamically controlled bias current flows are operating in weak inversion.
Claim 9
Dependent Claim
33 words
An integrated circuit according to claim 7 wherein the constant transconductance bias means maintains the current ratio of the first current source to the second current source equal to a predetermined constant value.
Claim 10
Dependent Claim
46 words
An integrated circuit according to claim 8 wherein said predetermined constant value is equal to the ratio of device transconductance parameter of the FETs through which the monitored bias current flows and device transconductance parameter of the FETs through which the dynamically controlled bias current flows.
Claim 11
Dependent Claim
27 words
An integrated circuit according to claim 1 further comprising a constant voltage source, electrically coupled to the constant transconductance bias means, for providing a bias voltage thereto.
Claim 12
Dependent Claim
27 words
An integrated circuit according to claim 1 further comprising a constant current source, electrically coupled to the constant transconductance bias means, for providing a bias current thereto.
Claim 13
Dependent Claim
136 words
An integrated circuit comprising: differential input means including a plurality of transistors of a first conductivity type having a first device transconductance parameter and a plurality of transistors of a second conductivity type having a second device transconductance parameter which is different from said first device transconductance parameter, said first and second plurality of transistors defining a first input and a second input for receiving a first and a second input signal and at least one output for providing an output signal which is proportional to the difference between the first and second input signals; and constant transconductance bias means, electrically connected to said differential input means, for dynamically controlling the differential input means to maintain constant transconductance of the differential input means, notwithstanding the different device transconductance parameters of said first and second conductivity transistors.
Claim 14
Dependent Claim
136 words
An integrated circuit comprising: differential input means including a plurality of transistors of a first conductivity type having a first device transconductance parameter and a plurality of transistors of a second conductivity type having a second device transconductance parameter which is different from said first device transconductance parameter, said first and second plurality of transistors defining a first input and a second input for receiving a first and a second input signal and at least one output for providing an output signal which is proportional to the difference between the first and second input signals; and constant transconductance bias means, electrically connected to said differential input means, for dynamically controlling the differential input means to maintain constant transconductance of the differential input means, notwithstanding the different device transconductance parameters of said first and second conductivity transistors.
Claim 15
Dependent Claim
62 words
An integrated circuit according to claim 12 further comprising: a first bias current source and a second bias current source, electrically connected to said differential input means and said constant transconductance bias means, wherein said constant transconductance bias means monitors one of the first and second bias current sources and dynamically controls the other of the first and second bias current sources.
Claim 16
Independent Claim
100 words
A method for operating an integrated circuit, the integrated circuit comprising a differential stage having a first differential pair of Field Effect Transistors (FETs) of a first conductivity type with a first bias current flowing therethrough and a second pair of differential FETs of a second conductivity type, electrically connected in parallel with the first pair of FETs, with a second bias current flowing therethrough, said method comprising the steps of: monitoring one of the first and second bias currents; and dynamically controlling the other of the first and second bias currents to maintain constant transconductance of the differential stage.
Claim 17
Independent Claim
100 words
A method for operating an integrated circuit, the integrated circuit comprising a differential stage having a first differential pair of Field Effect Transistors (FETs) of a first conductivity type with a first bias current flowing therethrough and a second pair of differential FETs of a second conductivity type, electrically connected in parallel with the first pair of FETs, with a second bias current flowing therethrough, said method comprising the steps of: monitoring one of the first and second bias currents; and dynamically controlling the other of the first and second bias currents to maintain constant transconductance of the differential stage.
Claim 18
Dependent Claim
34 words
A method according claim 14 wherein the monitored one of said first and second bias currents is a common mode voltage-dependent current and wherein the associated differential pair of FETs are of p-type conductivity.
Claim 19
Dependent Claim
38 words
A method according to claim 15 wherein the dynamically controlled other of said first and second bias currents is supplied by said constant transconductance bias means and wherein the associated differential pair of FETs are of n-type conductivity.
Claim 20
Dependent Claim
35 words
A method according to claim 14 wherein the monitored one of said first and second bias currents is a common mode voltage-dependent current and wherein the associated differential pair of FETs are of n-type conductivity.
Claim 21
Dependent Claim
38 words
A method according to claim 17 wherein the dynamically controlled other of the first and second bias currents is supplied by said constant transconductance bias means and wherein the associated differential pair of FETs are of p-type conductivity.
Claim 22
Dependent Claim
37 words
A method according to claim 14 further comprising the step of: limiting said dynamically controlled bias current to a predetermined maximum value when the FETs through which the monitored bias current flows are operating in weak inversion.
Claim 23
Dependent Claim
38 words
A method according to claim 19 further comprising the step of: limiting said monitored bias current to a second predetermined maximum value when the FETs through which the dynamically controlled bias current flows are operating in weak inversion.
Claim 24
Dependent Claim
36 words
A method according to claim 20 wherein said dynamically controlling step comprises the step of maintaining a ratio of the first predetermined maximum value to the second predetermined maximum value equal to a predetermined constant value.
Claim 25
Dependent Claim
45 words
A method according to claim 21 wherein said predetermined constant value is equal to the ratio of device transconductance parameter of the FETs through which the monitored bias current flows and device transconductance parameter of the FETs through which the dynamically controlled bias current flows.
References Cited (Backward Citations)
US5142244A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-23 | 1998-07-25 | 1999-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-23 | 2002-07-25 | 2003-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-23 | 2006-07-25 | 2007-01-24 | $7700.00 | Window Closed / Lapsed |