Minimizing the likelihood of slip between the instant a candidate for a break event is generated and the instant a microprocessor is instructed to perform a break, without missing breakpoints

Claim 2

In an in-circuit emulator on an integrated circuit chip having an input pin; an instruction pointer counter; a break logic; and, an abrupt break logic; an improvement comprising: first means for registering an instruction execution address; second means connected to said instruction pointer counter and to said first means for asserting a match output upon a condition that a contents of said instruction pointer counter matches said instruction execution address: third means connected to said second means for clocking a period of time, said period of time being an amount of time said break logic takes to arm in response to assertion of an arm signal; fourth means connected to said second means and to said third means for generating an abrupt break signal at said input pin upon a condition that said match output is asserted during said period of time; fifth means connected to said third means for generating an arm signal at said input pin upon a condition that said match output is not asserted during said period of time; sixth means connected to said input pin for activating said break logic in response to said arm signal on said input pin; and, seventh means connected to said input pin for activating said abrupt break logic in response to said abrupt break signal on said input pin.

Claim 3

In an in-circuit emulator on an integrated circuit chip having an input pin; an instruction pointer counter; a register for registering an instruction address; a match logic connected to said instruction pointer counter and to said register; said match logic asserting a match output upon a condition that a contents of said instruction pointer counter matches a contents of said register; a break logic; said break logic having an arm input; and, an abrupt break logic; said abrupt break logic having an abrupt break input; an improvement comprising: first means for delineating a fixed period of time at an output of said first means, said period of time being at least equal to an amount of time said break logic takes to arm after assertion of said arm input; second means connected to said input pin and to said arm input for activating said arm input in response to signals on said input pin; third means connecting said second means to said first means for starting said first means; fourth means for generating an abrupt break signal; fifth means for generating an arm signal; sixth means connected to said fourth and fifth means for selecting either said abrupt break signal or said arm signal in response to energization of a select input of said sixth means; and, seventh means for connecting said output of said first means to said input of said sixth means.

Claim 4

In an in-circuit emulator on an integrated circuit chip having an input pin; an instruction pointer counter; a register for registering an instruction address; a match logic connected to said instruction pointer counter and to said register; said match logic asserting a match output upon a condition that a contents of said instruction pointer counter matches a contents of said register; a break logic; said break logic having an arm input; and, an abrupt break logic; said abrupt break logic having an abrupt break input; an improvement comprising: first means for delineating a fixed period of time at an output of said first means, said period of time being at least equal to an amount of time said break logic takes to arm after assertion of said arm input; second means connected to said input pin and to said arm input for activating said arm input in response to signals on said input pin; third means connecting said second means to said first means for starting said first means; fourth means for generating an abrupt break signal; fifth means for generating an arm signal; sixth means connected to said fourth and fifth means for selecting either said abrupt break signal or said arm signal in response to energization of a select input of said sixth means; and, seventh means for connecting said output of said first means to said input of said sixth means.

Claim 5

In an in-circuit emulator comprising: an input pin; an instruction pointer counter; a match logic connected to said instruction pointer counter; said match logic matching said instruction pointer counter to an instruction execution address and for asserting a match output upon the condition that said instruction pointer counter matches said instruction execution address; a break logic; said break logic having an arm input; and, an abrupt break logic; said abrupt break logic having an abrupt break input; an improvement comprising; a counter that delineates a fixed period of time at an output of said counter, said period of time being at least equal to an amount of time said break logic takes to arm after assertion of said arm input; a break logic control connected to said input pin and to said arm input for activating said arm input in response to signals on said input pin; first means connecting said match output to said counter for starting said counter; abrupt break signature logic for generating an abrupt break signal; arm signature logic for generating an arm signal; and, a MUX connected to said abrupt break signature logic and to said arm signature logic for selecting either said abrupt break signal or said arm signal in response to energization of a select input of said MUX; said select input of said MUX being connected to said output of said counter.

Claim 6

In an in-circuit emulator comprising: an input pin; an instruction pointer counter; a match logic connected to said instruction pointer counter; said match logic matching said instruction pointer counter to an instruction execution address and for asserting a match output upon the condition that said instruction pointer counter matches said instruction execution address; a break logic; said break logic having an arm input; and, an abrupt break logic; said abrupt break logic having an abrupt break input; an improvement comprising; a counter that delineates a fixed period of time at an output of said counter, said period of time being at least equal to an amount of time said break logic takes to arm after assertion of said arm input; a break logic control connected to said input pin and to said arm input for activating said arm input in response to signals on said input pin; first means connecting said match output to said counter for starting said counter; abrupt break signature logic for generating an abrupt break signal; arm signature logic for generating an arm signal; and, a MUX connected to said abrupt break signature logic and to said arm signature logic for selecting either said abrupt break signal or said arm signal in response to energization of a select input of said MUX; said select input of said MUX being connected to said output of said counter.

Claim 7

In an in-circuit emulator on an integrated circuit chip having an input pin; an instruction pointer counter (IP counter); a break logic; an abrupt break logic; a method comprising steps of: A. comparing said instruction pointer counter to an instruction execution address; B. asserting a match output upon a condition that said instruction pointer counter matches said instruction execution address; C. starting a counter that once started runs a period of time and then is shut off, said period of time being an amount of time said break logic takes to arm in response to an arm signal; D. generating said abrupt break signal at said input pin upon a condition that said match output is asserted during said period of time; E. generating an arm signal at said input pin upon a condition that said match output is not asserted during said period of time; F. activating said break logic in response to said arm signal on said input pin; and, G. activating said abrupt break logic in response to said abrupt break signal on said input pin.

Claim 8

In an in-circuit emulator on an integrated circuit chip having an input pin; an instruction pointer counter (IP counter); a break logic; an abrupt break logic; a method comprising steps of: A. comparing said instruction pointer counter to an instruction execution address; B. asserting a match output upon a condition that said instruction pointer counter matches said instruction execution address; C. starting a counter that once started runs a period of time and then is shut off, said period of time being an amount of time said break logic takes to arm in response to an arm signal; D. generating said abrupt break signal at said input pin upon a condition that said match output is asserted during said period of time; E. generating an arm signal at said input pin upon a condition that said match output is not asserted during said period of time; F. activating said break logic in response to said arm signal on said input pin; and, G. activating said abrupt break logic in response to said abrupt break signal on said input pin.