Patent US5383080A successfully refreshed from Google Patents.
US5383080A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit having voltage limiter circuit
Assignee: Micron Memory Japan Ltd
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Filing: 1992-07-24
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Granted: 1995-01-17
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Expires: 2012-07-24
Abstract
Abstract A voltage limiter circuit is disposed in a semiconductor IC chip in order to reduce an operating voltage of an internal circuit of a scaled-down element. A small capacitance of a Vcc wiring by the disposition constitutes a resonance circuit together with an inductance of the Vcc wiring. Resonance at the resonance circuit causes large variation of a supply current and noise. An additional capacitance is connected between the Vcc wiring and a Vss wiring in order to suppress the variation and noise. The capacitance is formed by a PN junction and is connected in series to a damping resistance.
Inventors
- 👤 Jun Etoh
- 👤 Masakazu Aoki
- 👤 Masashi Horiguchi
- 👤 Shigeki Ueda
- 👤 Hitoshi Tanaka
- 👤 Kazuhiko Kajigaya
- 👤 Tsugio Takahashi
- 👤 Hiroshi Kawamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:34
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/147; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/462; G05F1/465; H; H10; H10D; H10D89/00; H10D89/60
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
105 words
A semiconductor integrated circuit comprising: a high-potential input terminal and a low-potential input terminal; a voltage limiter circuit adapted to be supplied with a supply voltage between said high-potential input terminal and said low-potential input terminal to generate a limited operating voltage smaller than the supply voltage; an inner circuit adapted to be supplied with said limited operating voltage; a capacitance connected between said high-potential input terminal and said low-potential input terminal so as to suppress a large variation of a supply current; and a resistance connected in series to said capacitance, wherein said capacitance is formed by a PN junction in a semiconductor chip.
Claim 2
Dependent Claim
105 words
A semiconductor integrated circuit comprising: a high-potential input terminal and a low-potential input terminal; a voltage limiter circuit adapted to be supplied with a supply voltage between said high-potential input terminal and said low-potential input terminal to generate a limited operating voltage smaller than the supply voltage; an inner circuit adapted to be supplied with said limited operating voltage; a capacitance connected between said high-potential input terminal and said low-potential input terminal so as to suppress a large variation of a supply current; and a resistance connected in series to said capacitance, wherein said capacitance is formed by a PN junction in a semiconductor chip.
Claim 3
Dependent Claim
24 words
A semiconductor integrated circuit according to claim 1, wherein said PN junction is formed of a P-type semiconductor substrate and an N-type diffusion layer.
Claim 4
Dependent Claim
24 words
A semiconductor integrated circuit according to claim 1, wherein said PN junction is formed of a P-type well layer and an N-type diffusion layer.
Claim 5
Dependent Claim
22 words
A semiconductor integrated circuit according to claim 1, wherein said PN junction is formed along an external edge of a semiconductor chip.
Claim 6
Dependent Claim
24 words
A semiconductor integrated circuit according to claim 1, wherein said PN junction is formed of an N-type well layer and a P-type diffusion layer.
Claim 7
Dependent Claim
22 words
A semiconductor integrated circuit according to claim 5, wherein said PN junction is formed along an external edge of a semiconductor chip.
Claim 8
Dependent Claim
130 words
A semiconductor integrated circuit comprising: a high-potential input terminal and a low-potential input terminal; a voltage limiter circuit adapted to be supplied with a supply voltage between said high-potential input terminal and said low-potential input terminal to generate a limited operating voltage smaller than the supply voltage; an inner circuit adapted to be supplied with said limited operating voltage; and a capacitance connected between said high-potential input terminal and said low-potential input terminal so as to suppress a large variation of a supply current, wherein said capacitance is formed by an overlapping arrangement of a first lead connected to said high-potential input terminal and a second lead connected to said low-potential input terminal, said first and second leads corresponding to inner leads overlying a main surface of a semiconductor chip.
Claim 9
Dependent Claim
130 words
A semiconductor integrated circuit comprising: a high-potential input terminal and a low-potential input terminal; a voltage limiter circuit adapted to be supplied with a supply voltage between said high-potential input terminal and said low-potential input terminal to generate a limited operating voltage smaller than the supply voltage; an inner circuit adapted to be supplied with said limited operating voltage; and a capacitance connected between said high-potential input terminal and said low-potential input terminal so as to suppress a large variation of a supply current, wherein said capacitance is formed by an overlapping arrangement of a first lead connected to said high-potential input terminal and a second lead connected to said low-potential input terminal, said first and second leads corresponding to inner leads overlying a main surface of a semiconductor chip.
Claim 10
Dependent Claim
87 words
A semiconductor integrated circuit comprising: a high-potential input terminal and a low-potential input terminal; a voltage limiter circuit applied with a supply voltage between said high-potential input terminal and said low-potential input terminal to generate a limited operating voltage smaller than the supply voltage; an inner circuit supplied with said limited operating voltage; and a capacitance connected between said high-potential input terminal and said low-potential input terminal to suppress large variation of a supply current, said capacitance being formed by a PN junction in a semiconductor chip.
Claim 11
Dependent Claim
87 words
A semiconductor integrated circuit comprising: a high-potential input terminal and a low-potential input terminal; a voltage limiter circuit applied with a supply voltage between said high-potential input terminal and said low-potential input terminal to generate a limited operating voltage smaller than the supply voltage; an inner circuit supplied with said limited operating voltage; and a capacitance connected between said high-potential input terminal and said low-potential input terminal to suppress large variation of a supply current, said capacitance being formed by a PN junction in a semiconductor chip.
Claim 12
Dependent Claim
24 words
A semiconductor integrated circuit according to claim 8, wherein said PN junction is formed of an N-type well layer and a P-type diffusion layer.
Claim 13
Dependent Claim
24 words
A semiconductor integrated circuit according to claim 8, wherein said PN junction is formed of a P-type semiconductor substrate and an N-type diffusion layer.
Claim 14
Dependent Claim
24 words
A semiconductor integrated circuit according to claim 8, wherein said PN junction is formed of a P-type well layer and an N-type diffusion layer.
Claim 15
Dependent Claim
22 words
A semiconductor integrated circuit according to claim 8, wherein said PN junction is formed along an external edge of a semiconductor chip.
Claim 16
Dependent Claim
40 words
A semiconductor integrated circuit according to claim 5, wherein said N-type well layer is lightly doped with an impurity, said P-type diffusion layer is heavily doped with an impurity, and said resistor is formed by said lightly doped well layer.
Claim 17
Dependent Claim
40 words
A semiconductor integrated circuit according to claim 2, wherein said N-type diffusion layer is heavily doped with an impurity, said P-type semiconductor substrate is lightly doped with an impurity, and said resistor is formed by said lightly doped semiconductor substrate.
Claim 18
Dependent Claim
40 words
A semiconductor integrated circuit according to claim 13, wherein said P-type well layer is lightly doped with an impurity, said N-type diffusion layer is heavily doped with an impurity, and said resistor is formed by said lightly doped well layer.
Claim 19
Dependent Claim
23 words
A semiconductor integrated circuit according to claim 3, wherein the main surface of said semiconductor chip is the front face of the chip.
Claim 20
Dependent Claim
23 words
A semiconductor integrated circuit according to claim 7, wherein the main surface of said semiconductor chip is the rear face of the chip.
Claim 21
Dependent Claim
30 words
A semiconductor integrated circuit according to claim 9, wherein said N-type well layer is lightly doped with an impurity and said P-type diffusion layer is heavily doped with an impurity.
Claim 22
Dependent Claim
30 words
A semiconductor integrated circuit according to claim 10, wherein said N-type diffusion layer is heavily doped with an impurity and said P-type semiconductor substrate is lightly doped with an impurity.
Claim 23
Dependent Claim
30 words
A semiconductor integrated circuit according to claim 11, wherein said P-type well layer is lightly doped with an impurity and said N-type diffusion layer is heavily doped with an impurity.
Claim 24
Dependent Claim
129 words
A semiconductor integrated circuit formed on a semiconductor chip comprising: a high-potential input terminal and a low-potential input terminal; a voltage limiter circuit adapted to be supplied with a supply voltage between said high-potential input terminal and said low-potential input terminal to generate a limited operating voltage smaller than the supply voltage, said voltage limiter circuit having a capacitance inherently built-in via supply wirings coupled thereto on the chip; an inner circuit adapted to be supplied with said limited operating voltage; an additional capacitance connected between said high-potential input terminal and said low-potential input terminal so as to suppress a large variation of a supply current; and a resistance connected in series to said capacitance, wherein said additional capacitance is formed by a PN junction in said semiconductor chip.
Claim 25
Dependent Claim
129 words
A semiconductor integrated circuit formed on a semiconductor chip comprising: a high-potential input terminal and a low-potential input terminal; a voltage limiter circuit adapted to be supplied with a supply voltage between said high-potential input terminal and said low-potential input terminal to generate a limited operating voltage smaller than the supply voltage, said voltage limiter circuit having a capacitance inherently built-in via supply wirings coupled thereto on the chip; an inner circuit adapted to be supplied with said limited operating voltage; an additional capacitance connected between said high-potential input terminal and said low-potential input terminal so as to suppress a large variation of a supply current; and a resistance connected in series to said capacitance, wherein said additional capacitance is formed by a PN junction in said semiconductor chip.
Claim 26
Dependent Claim
37 words
A semiconductor integrated circuit according to claim 21, wherein said PN junction is formed of a lightly doped N-type well layer and a heavily doped P-type diffusion layer, said resistance being formed by said N-type well layer.
Claim 27
Dependent Claim
36 words
A semiconductor integrated circuit according to claim 21, wherein said PN junction is formed of a lightly doped P-type semiconductor substrate and a heavily doped N-type diffusion layer, said resistance being formed by said semiconductor substrate.
Claim 28
Dependent Claim
37 words
A semiconductor integrated circuit according to claim 21, wherein said PN junction is formed of a lightly doped P-type well layer and a heavily doped N-type diffusion layer, said resistance being formed by said P-type well layer.
Claim 29
Dependent Claim
22 words
A semiconductor integrated circuit according to claim 21, wherein said PN junction is formed along an external edge of a semiconductor chip.
References Cited (Backward Citations)
US4930112A
Cited
US4731719A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-01-16 | 1998-07-18 | 1999-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-16 | 2002-07-18 | 2003-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-16 | 2006-07-18 | 2007-01-17 | $7700.00 | Window Closed / Lapsed |