US5382840A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog delay circuit configuration
Assignee: Siemens AG
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Filing: 1992-09-30
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Granted: 1995-01-17
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Expires: 2012-09-30
Abstract
Abstract An analog delay circuit configuration includes a switching stage. A capacitor is connected upstream of the switching stage. A controlled current source has a current being definitive for a charging state of the capacitor. The current source is clocked with a pulse-to-interval ratio of less than 1. A current mirror configuration reduces the current of the current source. An inverter stage is coupled to the current mirror configuration and has an output side connected to the capacitor.
Inventors
- 👤 Johann Massoner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:38
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/133; H03K2005/00013; H03K2005/0015; H03K2005/00195
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
77 words
An analog delay circuit configuration, comprising a switching stage, a capacitor connected upstream of said switching stage, a controlled current source having a current being definitive for a charging state of said capacitor, said current source being clocked with a pulse-to-interval ratio of less than 1, a current mirror configuration reducing the current of said current source, and an inverter stage being coupled to said current mirror configuration and having an output side connected to said capacitor.
Claim 2
Dependent Claim
77 words
An analog delay circuit configuration, comprising a switching stage, a capacitor connected upstream of said switching stage, a controlled current source having a current being definitive for a charging state of said capacitor, said current source being clocked with a pulse-to-interval ratio of less than 1, a current mirror configuration reducing the current of said current source, and an inverter stage being coupled to said current mirror configuration and having an output side connected to said capacitor.
Claim 3
Dependent Claim
26 words
The configuration according to claim 1, wherein said clocked current source includes a series circuit of a transistor connected as a resistor and a switching transistor.
Claim 4
Dependent Claim
22 words
The configuration according to claim 1, wherein said current mirror configuration includes a current mirror for a charging circuit of said capacitor.
Claim 5
Dependent Claim
22 words
The configuration according to claim 1, wherein said current mirror configuration includes a current mirror for a discharging circuit of said capacitor.
Claim 6
Dependent Claim
30 words
The configuration according to claim 1, wherein said current mirror configuration includes a current mirror for a charging circuit and a current mirror for a discharging circuit of said capacitor.
Claim 7
Dependent Claim
16 words
The configuration according to claim 1, including a Schmitt trigger configuration connected downstream of said capacitor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-16 | 1998-07-18 | 1999-01-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-16 | 2002-07-18 | 2003-01-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-16 | 2006-07-18 | 2007-01-17 | $7700.00 | Window Closed / Lapsed |