US5381544A
Expired / Lapsed
US
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Copyback memory system and cache memory controller which permits access while error recovery operations are performed
Assignee: Hitachi Ltd
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Filing: 1992-01-17
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Granted: 1995-01-10
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Expires: 2012-01-17
Abstract
Abstract A cache memory system for controlling a cache memory. The cache memory system is connected to a central processing unit and a main memory and the cache memory system is controlled to operate in a copyback operation mode. The cache memory system includes the cache memory which operates as cache memory to the central processing unit and a control circuit, responsive to detection of an error in the cache memory, for suspending an updating operation of an entry in the cache memory in which the error was detected, controlling access to valid entries in the cache memory, and causing the cache memory to operate as cache memory only when access from the central processing unit hits the valid entries of the cache memory.
Inventors
- 👤 Koichi Okazawa
- 👤 Kazushi Kobayashi
- 👤 Ichiharu Aburano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 01:13
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/88; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
120 words
A cache memory system connected to a central processing unit and a main memory, wherein said cache memory system is controlled to operate in a copyback operation mode, said system comprising: a cache memory for operating as cache memory to said central processing unit; and control means, coupled to said cache memory and responsive to detection of an error in said cache memory by error detection means, for suspending an updating operation of an entry in said cache memory in which said error was detected, controlling access to valid entries in said cache memory, and controlling said cache memory to operate as cache memory only when access from said central processing unit hits said valid entries of said cache memory.
Claim 2
Dependent Claim
120 words
A cache memory system connected to a central processing unit and a main memory, wherein said cache memory system is controlled to operate in a copyback operation mode, said system comprising: a cache memory for operating as cache memory to said central processing unit; and control means, coupled to said cache memory and responsive to detection of an error in said cache memory by error detection means, for suspending an updating operation of an entry in said cache memory in which said error was detected, controlling access to valid entries in said cache memory, and controlling said cache memory to operate as cache memory only when access from said central processing unit hits said valid entries of said cache memory.
Claim 3
Dependent Claim
136 words
A cache memory system connected to a central processing unit and main memory, wherein said cache memory system is controlled to operate in a copyback operation mode, said system comprising: a cache memory for operating as cache memory to said central processing unit; error detection means for detecting an error when said cache memory is accessed; and control means coupled to said cache memory and said error detection means, for suspending, after an error is detected by said error detection means, an updating operation of an entry in said cache memory in which said error is detected, controlling valid entries of said cache memory existing when said error is detected and controlling said cache memory to operate as cache memory only when access from said central processing unit hits said valid entries of said cache memory.
Claim 4
Dependent Claim
136 words
A cache memory system connected to a central processing unit and main memory, wherein said cache memory system is controlled to operate in a copyback operation mode, said system comprising: a cache memory for operating as cache memory to said central processing unit; error detection means for detecting an error when said cache memory is accessed; and control means coupled to said cache memory and said error detection means, for suspending, after an error is detected by said error detection means, an updating operation of an entry in said cache memory in which said error is detected, controlling valid entries of said cache memory existing when said error is detected and controlling said cache memory to operate as cache memory only when access from said central processing unit hits said valid entries of said cache memory.
Claim 5
Dependent Claim
46 words
A cache memory system according to claim 1 wherein said control means comprises: means for resuming said suspended updating operation of the entry in said cache memory in response to instructions from said central processing unit after said error in said cache memory has been corrected.
Claim 6
Dependent Claim
46 words
A cache memory system according to claim 2 wherein said control means comprises: means for resuming said suspended updating operation of the entry in said cache memory in response to instructions from said central processing unit after said error in said cache memory has been corrected.
Claim 7
Dependent Claim
157 words
A cache memory system connected to a central processing unit and a main memory wherein said cache memory system is controlled to operate in a copyback operation mode, said system comprising: a cache memory for operating as a cache memory to said central processing unit; and control means, coupled to said cache memory, for allowing, after an error in said cache memory is detected by error detection means where said cache memory is accessed, access from said central processing unit to valid entries of said cache memory existing at the time of occurrence of said error when the access hits a valid entry in said cache memory, inhibiting access from said central processing unit to said cache memory when the access miss-hits an entry in said cache memory and allowing said central processing unit to access said main memory without replacing the contents of said cache memory when the access miss-hits an entry in said cache memory.
Claim 8
Dependent Claim
157 words
A cache memory system connected to a central processing unit and a main memory wherein said cache memory system is controlled to operate in a copyback operation mode, said system comprising: a cache memory for operating as a cache memory to said central processing unit; and control means, coupled to said cache memory, for allowing, after an error in said cache memory is detected by error detection means where said cache memory is accessed, access from said central processing unit to valid entries of said cache memory existing at the time of occurrence of said error when the access hits a valid entry in said cache memory, inhibiting access from said central processing unit to said cache memory when the access miss-hits an entry in said cache memory and allowing said central processing unit to access said main memory without replacing the contents of said cache memory when the access miss-hits an entry in said cache memory.
Claim 9
Dependent Claim
180 words
A cache memory controller for controlling, under control of a central processing unit, a cache memory for storing a copy of a portion of contents of a main memory and a tag memory for storing address information of the copy stored in said cache memory, comprising: tag memory control means for controlling read and write operations of said tag memory; cache memory control means for controlling read and write operations of said cache memory; error detecting means, coupled to said cache memory and said tag memory, for detecting an error in said cache memory and said tag memory; error retaining means, coupled to said error detecting means, for retaining, when an error is detected by said error detecting means, error information indicating occurrence of the error; and sequence control means, coupled to said tag memory control means, said cache memory control means said error retaining means for controlling, under the control of said central processing unit, operations of said tag memory control means and said cache memory control means according to said error information retained in said error retaining means.
Claim 10
Dependent Claim
180 words
A cache memory controller for controlling, under control of a central processing unit, a cache memory for storing a copy of a portion of contents of a main memory and a tag memory for storing address information of the copy stored in said cache memory, comprising: tag memory control means for controlling read and write operations of said tag memory; cache memory control means for controlling read and write operations of said cache memory; error detecting means, coupled to said cache memory and said tag memory, for detecting an error in said cache memory and said tag memory; error retaining means, coupled to said error detecting means, for retaining, when an error is detected by said error detecting means, error information indicating occurrence of the error; and sequence control means, coupled to said tag memory control means, said cache memory control means said error retaining means for controlling, under the control of said central processing unit, operations of said tag memory control means and said cache memory control means according to said error information retained in said error retaining means.
Claim 11
Dependent Claim
72 words
A cache memory controller according to claim 6, wherein said sequence control means inhibits write operations of new address information into said tag memory when error information indicating occurrence of an error is retained in said error retaining means and allows read and write operations of said cache memory when access from said central processing unit hits address information stored in said tag memory corresponding to valid entries in said cache memory.
Claim 12
Dependent Claim
31 words
A cache memory controller according to claim 6 wherein said sequence control comprises: means for allowing said central processing unit to alter said error information retained in said error retaining means.
Claim 13
Dependent Claim
50 words
A cache memory controller according to claim 7 wherein said sequences control means comprises: means for allowing said central processing unit to alter said error information retained in said error retaining means; and means for resuming said inhibited write operations after said error in said cache memory has been corrected.
Claim 14
Independent Claim
101 words
A method of controlling a cache memory connected to a central processing unit and a main memory comprising the steps of: outputting said cache memory in a copyback operation mode as cache memory to said central processing unit; in response to detection of an error in said cache memory, suspending an updating operation of an entry in said cache memory in which said error was detected; controlling access to valid entries in said cache memory; and causing said cache memory to operate as cache memory only when access from said central processing unit hits said valid entries of said cache memory.
Claim 15
Independent Claim
101 words
A method of controlling a cache memory connected to a central processing unit and a main memory comprising the steps of: outputting said cache memory in a copyback operation mode as cache memory to said central processing unit; in response to detection of an error in said cache memory, suspending an updating operation of an entry in said cache memory in which said error was detected; controlling access to valid entries in said cache memory; and causing said cache memory to operate as cache memory only when access from said central processing unit hits said valid entries of said cache memory.
Claim 16
Independent Claim
125 words
A method of controlling a cache memory connected to a central processing unit and main memory comprising the steps of: operating said cache memory in a copyback operation mode as cache memory to said central processing unit; detecting an error when said cache memory is accessed; suspending, after an error is detected by said error detecting step, an updating operation of an entry in said cache memory in which said error was detected; updating an entry in said cache memory in which said error is detected; controlling valid entries of said cache memory existing when said error is detected; and causing said cache memory to operate as cache memory only when access from said central processing unit hits said valid entries of said cache memory.
Claim 17
Independent Claim
125 words
A method of controlling a cache memory connected to a central processing unit and main memory comprising the steps of: operating said cache memory in a copyback operation mode as cache memory to said central processing unit; detecting an error when said cache memory is accessed; suspending, after an error is detected by said error detecting step, an updating operation of an entry in said cache memory in which said error was detected; updating an entry in said cache memory in which said error is detected; controlling valid entries of said cache memory existing when said error is detected; and causing said cache memory to operate as cache memory only when access from said central processing unit hits said valid entries of said cache memory.
Claim 18
Dependent Claim
47 words
A method of controlling a cache memory according to claim 10 further comprising the steps of: resuming said suspended updating operation of the entry in said cache memory in response to instructions from said central processing unit after said error in said cache memory has been corrected.
Claim 19
Dependent Claim
47 words
A method of controlling a cache memory according to claim 11 further comprising the steps of: resuming said suspended updating operation of the entry in said cache memory in response to instructions from said central processing unit after said error in said cache memory has been corrected.
Claim 20
Independent Claim
138 words
A method of controlling a cache memory connected to a central processing unit and a main memory comprising the steps of: operating said cache memory in a copyback operation mode as cache memory to said central processing unit; allowing, after an error in said cache memory is detected when said cache memory is accessed, access from said central processing unit to valid entries of said cache memory existing at the time of occurrence of said error when the access hits a valid entry in said cache memory; inhibiting access from said central processing unit to said cache memory when the access miss-hits an entry in said cache memory; and allowing said central processing unit to have said main memory accessed without replacing the contents of said cache memory when the access miss-hits an entry in said cache memory.
Claim 21
Independent Claim
138 words
A method of controlling a cache memory connected to a central processing unit and a main memory comprising the steps of: operating said cache memory in a copyback operation mode as cache memory to said central processing unit; allowing, after an error in said cache memory is detected when said cache memory is accessed, access from said central processing unit to valid entries of said cache memory existing at the time of occurrence of said error when the access hits a valid entry in said cache memory; inhibiting access from said central processing unit to said cache memory when the access miss-hits an entry in said cache memory; and allowing said central processing unit to have said main memory accessed without replacing the contents of said cache memory when the access miss-hits an entry in said cache memory.
Claim 22
Independent Claim
129 words
A method of controlling by a central processing unit, a cache memory, operated in the copyback operation mode, for storing a copy of a portion of contents of a main memory and a tag memory for storing address information of the copy stored in said cache memory, said method comprising the steps of: controlling read and write operations of said tag memory; controlling read and write operations of said cache memory; detecting an error in said cache memory and said tag memory; retaining, when an error is detected by said error detecting means, error information indicating occurrence of the error; and controlling, under the control of said central processing unit, operations of said tag memory control means and said cache memory control means according to said retained error information.
Claim 23
Independent Claim
129 words
A method of controlling by a central processing unit, a cache memory, operated in the copyback operation mode, for storing a copy of a portion of contents of a main memory and a tag memory for storing address information of the copy stored in said cache memory, said method comprising the steps of: controlling read and write operations of said tag memory; controlling read and write operations of said cache memory; detecting an error in said cache memory and said tag memory; retaining, when an error is detected by said error detecting means, error information indicating occurrence of the error; and controlling, under the control of said central processing unit, operations of said tag memory control means and said cache memory control means according to said retained error information.
Claim 24
Dependent Claim
77 words
A method of controlling a cache memory according to claim 15 wherein said controlling step comprises the step of: inhibiting write operations of new address information into said tag memory when error information indicating occurrence of an error is retained by said retaining step; and allowing read and write operations of said cache memory when access from said central processing unit hits address information stored in said tag memory corresponding to valid entries in said cache memory.
Claim 25
Dependent Claim
31 words
A method of controlling a cache memory according to claim 15 further comprising the steps of: allowing said central processing unit to alter said error information retained by said retaining step.
Claim 26
Dependent Claim
50 words
A method of controlling a cache memory according to claim 16 further comprising the steps of: allowing said central processing unit to alter said error information retained by said retaining step in said error; and resuming said inhibited write operations after said error in said cache memory has been corrected.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-09 | 1998-07-11 | 1999-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-09 | 2002-07-11 | 2003-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-09 | 2006-07-11 | 2007-01-10 | $7700.00 | Window Closed / Lapsed |