Semiconductor memory device and an operating method of the same

Claim 2

A semiconductor memory device comprising: a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing data; and a plurality of bit lines provided corresponding to said plurality of columns and each connected to memory cells in the corresponding column, said plurality of bit lines being divided into a plurality of bit line groups each including a predetermined number of bit lines, said plurality of bit line groups being classified into n main groups; n input/output line groups provided corresponding to said n main groups and each including a predetermined number of input/output lines; a plurality of connecting means provided corresponding to said plurality of bit line groups and each connected between the corresponding bit line group and the corresponding input/output line group; and column selecting means for selectively generating a plurality of selecting signals corresponding to said plurality of connecting means for selecting any of said plurality of bit line groups; wherein each of said plurality of connecting means is activated in response to the corresponding selecting signal and connects each bit line in the corresponding bit line group to each input/output line in the corresponding input/output line group; and said column selecting means includes means for activating a plurality of connecting means connected to different input/output line groups in said memory array at the same time or with a predetermined time difference.

Claim 3

The semiconductor memory device according to claim 1, further comprising: a global input/output line group provided commonly to said n input/output line groups and including a predetermined number of input/output lines; switching means for selectively connecting each input/output line in said n input/output line groups to the corresponding input/output line in said global input/output line group; and input/output line selecting means for sequentially selecting the respective input/output lines in said global input/output line group.

Claim 4

The semiconductor- memory device according to claim 2, further comprising: address counter means having a first mode for generating an address signal indicative of an address which sequentially changes from an initial address, and a second mode for generating an address signal indicative of an address which circulates within a predetermined range; wherein said column selecting means is responsive to a part of said address signal generated from said address counter means to select and activate any ones of said plurality of connecting means at the same time or with a predetermined time difference, and said input/output line selecting means is responsive to the remaining part of said address signal generated from said address counter means to sequentially select data corresponding to said input/output lines in said global input/output line group.

Claim 5

The semiconductor memory device according to claim 3, further comprising: a plurality of word lines provided corresponding to said plurality of rows and each connected to memory cells in the corresponding row; row selecting means for selecting and activating any one of said plurality of word lines; and control means for activating said address counter means while maintaining a state in which one of said word lines is activated by said row selecting means.

Claim 6

The semiconductor memory device according to claim 2, wherein each of said bit lines includes a bit line pair, each of said input/output lines in said n input/output line groups includes an input/output line pair, and each of said input/output lines in said global input/output line group includes an input/output line pair.

Claim 7

A semiconductor memory device, comprising: a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing data and a plurality of bit lines provided corresponding to said plurality of columns and each connected to memory cells in the corresponding column, said plurality of bit lines being divided into a plurality of bit line groups each including a predetermined number of bit lines; n input/output line groups each including a predetermined number of input/output lines; n connecting means groups provided corresponding to said n input/output line groups, each of said n connecting means groups including a plurality of connecting means, provided corresponding to said plurality of bit line groups and each connected between the corresponding bit line group and the corresponding input/output line group; and column selecting means for selectively generating a plurality of selecting signals corresponding to said plurality of connecting means in each connecting means group for selecting any of said plurality of bit line groups, each of said plurality of connecting means in each connecting means group being activated in response to the corresponding selecting signal and connecting each bit line in the corresponding bit line group to each input/output line in the corresponding input/output line group, and said column selecting means including means for activating a plurality of connecting means connected to different input/output line groups in said memory array at the same time or with a predetermined time difference.

Claim 8

A semiconductor memory device, comprising: a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing data and a plurality of bit lines provided corresponding to said plurality of columns and each connected to memory cells in the corresponding column, said plurality of bit lines being divided into a plurality of bit line groups each including a predetermined number of bit lines; n input/output line groups each including a predetermined number of input/output lines; n connecting means groups provided corresponding to said n input/output line groups, each of said n connecting means groups including a plurality of connecting means, provided corresponding to said plurality of bit line groups and each connected between the corresponding bit line group and the corresponding input/output line group; and column selecting means for selectively generating a plurality of selecting signals corresponding to said plurality of connecting means in each connecting means group for selecting any of said plurality of bit line groups, each of said plurality of connecting means in each connecting means group being activated in response to the corresponding selecting signal and connecting each bit line in the corresponding bit line group to each input/output line in the corresponding input/output line group, and said column selecting means including means for activating a plurality of connecting means connected to different input/output line groups in said memory array at the same time or with a predetermined time difference.

Claim 9

The semiconductor memory device according to claim 6, further comprising input/output line selecting means for sequentially selecting the respective input/output lines in said n input/output line groups.

Claim 10

The semiconductor memory device according to claim 7, further comprising: address counter means having a first mode for generating an address signal indicative of an address which sequentially changes from an initial address, and a second mode for generating an address signal indicative of an address which circulates within a predetermined range; wherein said column selecting means is responsive to a part of said address signal generated from said address counter means to select and activate any ones of said plurality of connecting means at the same time or with a predetermined time difference, and said input/output line selecting means is responsive to a part of said address signal generated from said address counter means to sequentially select data corresponding to said input/output lines in said n input/output line groups.

Claim 11

The semiconductor memory device according to claim 8, further comprising: a plurality of word lines provided corresponding to said plurality of rows and each connected to memory cells in the corresponding row; row selecting means for selecting and activating any one of said plurality of word lines; and control means for activating said address counter means while maintaining a state in which one of said word lines is activated by said row selecting means.

Claim 12

The semiconductor memory device according to claim 7, wherein each of said bit lines includes a bit line pair, and each of said input/output lines in said n input/output line groups includes an input/output line pair.

Claim 13

A semiconductor memory device, comprising: a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing data and a plurality of bit lines provided corresponding to said plurality of columns and each connected to memory cells in the corresponding column, said plurality of bit lines being divided into a plurality of bit line groups each including a predetermined number of bit lines, said plurality of bit line groups being classified into n main groups, said bit line groups in said n main groups being disposed alternately; n input/output line groups provided corresponding to said n main groups and each including a predetermined number of input/output lines; a plurality of connecting means provided corresponding to said plurality of bit line groups, and each connected between the corresponding bit line group and the corresponding input/output line group; column selecting means for selectively generating a plurality of selecting signals corresponding to said plurality of connecting means for selecting any of said plurality of bit line groups, each of said plurality of connecting means being activated in response to the corresponding selecting signal and connecting each bit line in the corresponding bit line group to each input/output line in the corresponding input/output line group, said column selecting means including means for activating a plurality of connecting means connected to different input/output line groups in said memory array at the same time or with a predetermined time difference; a global input/output line group provided commonly to said n input/output line groups and including a predetermined number of input/output lines; changing means for selectively connecting each input/output line in said n input/output line groups to the corresponding input/output line in said global input/output line group; and input/output line selecting means for sequentially selecting the respective input/output lines in said global input/output line group.

Claim 14

A semiconductor memory device, comprising: a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing data and a plurality of bit lines provided corresponding to said plurality of columns and each connected to memory cells in the corresponding column, said plurality of bit lines being divided into a plurality of bit line groups each including a predetermined number of bit lines, said plurality of bit line groups being classified into n main groups, said bit line groups in said n main groups being disposed alternately; n input/output line groups provided corresponding to said n main groups and each including a predetermined number of input/output lines; a plurality of connecting means provided corresponding to said plurality of bit line groups, and each connected between the corresponding bit line group and the corresponding input/output line group; column selecting means for selectively generating a plurality of selecting signals corresponding to said plurality of connecting means for selecting any of said plurality of bit line groups, each of said plurality of connecting means being activated in response to the corresponding selecting signal and connecting each bit line in the corresponding bit line group to each input/output line in the corresponding input/output line group, said column selecting means including means for activating a plurality of connecting means connected to different input/output line groups in said memory array at the same time or with a predetermined time difference; a global input/output line group provided commonly to said n input/output line groups and including a predetermined number of input/output lines; changing means for selectively connecting each input/output line in said n input/output line groups to the corresponding input/output line in said global input/output line group; and input/output line selecting means for sequentially selecting the respective input/output lines in said global input/output line group.

Claim 15

A semiconductor memory device comprising: n memory arrays disposed adjacently to each other, each of said n memory arrays including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing data, and a plurality of bit lines provided corresponding to said plurality of columns and each are connected to memory cells in the corresponding column, and said plurality of bit lines being divided into a plurality of bit line groups, each including a predetermined number of bit lines; n input/output line groups provided corresponding to said n memory arrays and each including a predetermined number of input/output lines, each located near one end of said plurality of bit line groups in the corresponding memory array and extending perpendicularly to each bit line; a plurality of connecting means provided corresponding to said plurality of bit line groups in said n memory arrays, and each are connected between the corresponding bit line group and the corresponding input/output line group; column selecting means for selectively generating a plurality of selecting signals corresponding to said plurality of connecting means for selecting any of said plurality of bit line groups in said n memory arrays; each of said plurality of connecting means being activated in response to the corresponding selecting signal and connecting each bit line in the corresponding bit line group to each input/output line in the corresponding input/output line group, said column selecting means including means for activating a plurality of connecting means connected to input/output line groups in different memory arrays at the same time or with a predetermined time difference; a global input/output line group provided commonly to said n input/output line groups and including a predetermined number of input/output lines; changing means for selectively connecting each input/output line in said n input/output line groups to the corresponding input/output line in said global input/output line group; and input/output line selecting means for sequentially selecting the respective input/output lines in said global input/output line group.

Claim 16

A semiconductor memory device comprising: n memory arrays disposed adjacently to each other, each of said n memory arrays including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing data, and a plurality of bit lines provided corresponding to said plurality of columns and each are connected to memory cells in the corresponding column, and said plurality of bit lines being divided into a plurality of bit line groups, each including a predetermined number of bit lines; n input/output line groups provided corresponding to said n memory arrays and each including a predetermined number of input/output lines, each located near one end of said plurality of bit line groups in the corresponding memory array and extending perpendicularly to each bit line; a plurality of connecting means provided corresponding to said plurality of bit line groups in said n memory arrays, and each are connected between the corresponding bit line group and the corresponding input/output line group; column selecting means for selectively generating a plurality of selecting signals corresponding to said plurality of connecting means for selecting any of said plurality of bit line groups in said n memory arrays; each of said plurality of connecting means being activated in response to the corresponding selecting signal and connecting each bit line in the corresponding bit line group to each input/output line in the corresponding input/output line group, said column selecting means including means for activating a plurality of connecting means connected to input/output line groups in different memory arrays at the same time or with a predetermined time difference; a global input/output line group provided commonly to said n input/output line groups and including a predetermined number of input/output lines; changing means for selectively connecting each input/output line in said n input/output line groups to the corresponding input/output line in said global input/output line group; and input/output line selecting means for sequentially selecting the respective input/output lines in said global input/output line group.

Claim 17

A semiconductor memory device, comprising: a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing data and a plurality of bit lines provided corresponding to said plurality of columns and each connected to memory cells in the corresponding column, said plurality of bit lines being divided into a plurality of first bit line groups each including a predetermined number of bit lines and a plurality of second bit line groups each including a predetermined number of bit lines; a first input/output line group including a predetermined number of input/output lines; a second input/outpour line group including a predetermined number of input/output lines; a plurality of first connecting means provided corresponding to said plurality of first bit line groups, and each connected between the corresponding first bit line group and said first input/output line group; a plurality of second connecting means provided corresponding to said plurality of second bit line groups, and each connected between the corresponding second bit line group and said second input/output line group; and column selecting means for selectively generating a plurality of selecting signals corresponding to said plurality of first and second connecting means for selecting any of said plurality of first and second bit line groups; each of said plurality of first connecting means being activated in response tip the corresponding selecting signal and connecting each bit line in the corresponding first bit line group to each input/output line in said first input/output line group, each of said plurality of second connecting means being activated in response to the corresponding selecting signal to be activated and connecting each bit line in the corresponding second bit line group to each input/output line in said second input/output line group, and said column selecting means including means for activating a plurality of connecting means connected to different input/output line groups in said memory array at the same time or with a predetermined time difference.

Claim 18

A semiconductor memory device, comprising: a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing data and a plurality of bit lines provided corresponding to said plurality of columns and each connected to memory cells in the corresponding column, said plurality of bit lines being divided into a plurality of first bit line groups each including a predetermined number of bit lines and a plurality of second bit line groups each including a predetermined number of bit lines; a first input/output line group including a predetermined number of input/output lines; a second input/outpour line group including a predetermined number of input/output lines; a plurality of first connecting means provided corresponding to said plurality of first bit line groups, and each connected between the corresponding first bit line group and said first input/output line group; a plurality of second connecting means provided corresponding to said plurality of second bit line groups, and each connected between the corresponding second bit line group and said second input/output line group; and column selecting means for selectively generating a plurality of selecting signals corresponding to said plurality of first and second connecting means for selecting any of said plurality of first and second bit line groups; each of said plurality of first connecting means being activated in response tip the corresponding selecting signal and connecting each bit line in the corresponding first bit line group to each input/output line in said first input/output line group, each of said plurality of second connecting means being activated in response to the corresponding selecting signal to be activated and connecting each bit line in the corresponding second bit line group to each input/output line in said second input/output line group, and said column selecting means including means for activating a plurality of connecting means connected to different input/output line groups in said memory array at the same time or with a predetermined time difference.

Claim 19

A semiconductor memory device, comprising: a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing data and a plurality of bit lines provided corresponding to said plurality of columns and each connected to memory cells in the corresponding column, said plurality of bit lines being divided into a plurality of bit line groups each including a predetermined number of bit lines; a first input/output line group including a predetermined number of input/output lines; a second input/output line group including a predetermined number of input/output lines; a plurality of first connecting means provided corresponding to said plurality of bit line groups, and each connected between the corresponding bit line group and said first input/output line group; a plurality of second connecting means provided corresponding to said plurality of bit line groups, and each connected between the corresponding bit line group and the second input/output line group; and column selecting means for selectively generating a plurality of selecting signals corresponding to said plurality of first and second connecting means for selecting any of said plurality of first and second connecting means; each of said plurality of first connecting means being activated in response to the corresponding selecting signal and connecting each bit line in the corresponding bit line group to each input/output line in said first input/output line group, each of said plurality of second connecting means being activated in response to the corresponding selecting signal and connecting each bit line in the corresponding bit line group to each input/output line in said second input/output line group, and said column selecting means including means for activating a plurality of connecting means connected to different input/output line groups in said memory array at the same time or with a predetermined time difference.

Claim 20

A semiconductor memory device, comprising: a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing data and a plurality of bit lines provided corresponding to said plurality of columns and each connected to memory cells in the corresponding column, said plurality of bit lines being divided into a plurality of bit line groups each including a predetermined number of bit lines; a first input/output line group including a predetermined number of input/output lines; a second input/output line group including a predetermined number of input/output lines; a plurality of first connecting means provided corresponding to said plurality of bit line groups, and each connected between the corresponding bit line group and said first input/output line group; a plurality of second connecting means provided corresponding to said plurality of bit line groups, and each connected between the corresponding bit line group and the second input/output line group; and column selecting means for selectively generating a plurality of selecting signals corresponding to said plurality of first and second connecting means for selecting any of said plurality of first and second connecting means; each of said plurality of first connecting means being activated in response to the corresponding selecting signal and connecting each bit line in the corresponding bit line group to each input/output line in said first input/output line group, each of said plurality of second connecting means being activated in response to the corresponding selecting signal and connecting each bit line in the corresponding bit line group to each input/output line in said second input/output line group, and said column selecting means including means for activating a plurality of connecting means connected to different input/output line groups in said memory array at the same time or with a predetermined time difference.

Claim 21

An operating method of a semiconductor memory device, including a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each store data and a plurality of bit lines provided corresponding to said plurality of columns and each connected to memory cells in the corresponding column, said plurality of bit lines being divided into a plurality of first bit line groups each including a predetermined number of bit lines and a plurality of second bit line groups each including a predetermined number of bit lines; a first input/output line group including a predetermined number of input/output lines; and a second input/output line group including a predetermined number of input/output lines, said method comprising the step of: connecting any one of said plurality of first bit line groups and any one of said plurality of second bit line groups to said first and second input/output line groups, respectively, at the same time or with a predetermined time difference.

Claim 22

An operating method of a semiconductor memory device, including a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each store data and a plurality of bit lines provided corresponding to said plurality of columns and each connected to memory cells in the corresponding column, said plurality of bit lines being divided into a plurality of first bit line groups each including a predetermined number of bit lines and a plurality of second bit line groups each including a predetermined number of bit lines; a first input/output line group including a predetermined number of input/output lines; and a second input/output line group including a predetermined number of input/output lines, said method comprising the step of: connecting any one of said plurality of first bit line groups and any one of said plurality of second bit line groups to said first and second input/output line groups, respectively, at the same time or with a predetermined time difference.

Claim 23

The operating method according to claim 15, wherein said semiconductor memory device further includes a global input/output line group including a predetermined number of input/output lines, said method further comprising the steps of: selectively connecting each input/output line in said first and second input/output line groups to the corresponding input/output line in said global input/output line group; and sequentially selecting the respective input/output lines in said global input/output line group.

Claim 24

An operating method of a semiconductor memory device including a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing data and a plurality of bit lines provided corresponding to said plurality of columns and each connected to memory cells in the corresponding column, said plurality of bit lines being divided into a plurality of bit line groups each including a predetermined number of bit lines, a first input/output line group including a predetermined number of input/output lines, a second input/output line group including a predetermined number of input/output lines, a plurality of first connecting means provided corresponding to said plurality of bit line groups and each connecting the corresponding bit line group to said first input/output line group, and a plurality of second connecting means provided corresponding to said plurality of bit line groups and each connecting the corresponding bit line group to said second input/output line group, said method comprising the step of: activating any one of said plurality of first connecting means and any one of said plurality of second connecting means at the same time or with a predetermined time difference.

Claim 25

An operating method of a semiconductor memory device including a memory array including a plurality of memory cells arranged in a plurality of rows and a plurality of columns and each storing data and a plurality of bit lines provided corresponding to said plurality of columns and each connected to memory cells in the corresponding column, said plurality of bit lines being divided into a plurality of bit line groups each including a predetermined number of bit lines, a first input/output line group including a predetermined number of input/output lines, a second input/output line group including a predetermined number of input/output lines, a plurality of first connecting means provided corresponding to said plurality of bit line groups and each connecting the corresponding bit line group to said first input/output line group, and a plurality of second connecting means provided corresponding to said plurality of bit line groups and each connecting the corresponding bit line group to said second input/output line group, said method comprising the step of: activating any one of said plurality of first connecting means and any one of said plurality of second connecting means at the same time or with a predetermined time difference.

Claim 26

The method according to claim 17, further comprising the step of: sequentially selecting the respective input/output lines in said first and second input/output line groups.