US5381085A
Expired / Lapsed
US
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Phase lock loop with self test circuitry and method for using the same
Assignee: Apple Inc
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Filing: 1993-07-06
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Granted: 1995-01-10
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Expires: 2013-07-06
Abstract
Abstract A built in self test circuit for testing a phase lock loop (11). The built in self test circuitry comprises a pulse circuit (13), an And gate (19), a counter circuit (23), and an output multiplexer (24). The phase lock loop (11) receives a reference signal and generates an output signal. The pulse circuit (13) receives the reference signal and generates a pulse having a duration some multiple of the output signal of the phase lock loop. The And gate (19) receives the pulse output by pulse circuit (13) and the output signal of the phase lock loop (11) generating a string of pulses having the frequency of the output signal of the phase lock loop (11) for the duration of the pulse output by the pulse circuit (13). The counter circuit (23) receives the string of pulses and generates a count of the pulses. The count is compared to an expected count to determine the accuracy of the phase lock loop (11).
Inventors
- 👤 Lynn R. Fischer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:55
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318392; G01R31/316; G06; G06F; G06F2201/00; G06F2201/88
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
99 words
A method for self testing a phase lock loop, the phase lock loop receiving a reference signal of a first frequency for generating an output signal of a second frequency, the method comprising: providing a pulse having a predetermined window of time which is a multiple of the period of the reference frequency; counting pulses of the output signal from the phase lock loop during said window of time; and comparing a count of said pulses from the phase lock loop against an expected count of pulses to determine accuracy of the output signal of the phase lock loop.
Claim 2
Independent Claim
99 words
A method for self testing a phase lock loop, the phase lock loop receiving a reference signal of a first frequency for generating an output signal of a second frequency, the method comprising: providing a pulse having a predetermined window of time which is a multiple of the period of the reference frequency; counting pulses of the output signal from the phase lock loop during said window of time; and comparing a count of said pulses from the phase lock loop against an expected count of pulses to determine accuracy of the output signal of the phase lock loop.
Claim 3
Dependent Claim
62 words
A method as recited in claim 1 wherein said providing a window of time step includes coupling the reference signal to a pulse circuit, said pulse circuit generating a pulse from the reference signal having a duration equal to the window of time thereby retaining a time relationship between said window of time and the output signal of the phase lock loop.
Claim 4
Dependent Claim
66 words
A method as recited in claim 2 wherein said coupling the reference frequency to a pulse circuit step includes: dividing the reference signal with a divide circuit thereby providing a signal of a third frequency having a period larger than the period of the reference signal; and forming said pulse with a gating circuit, said gating circuit being clocked with said signal of said third frequency.
Claim 5
Dependent Claim
44 words
A method as recited in claim 3 further including coupling said pulse and the output signal of the phase lock loop to an And gate thereby producing a series of pulses of the second frequency for a time equal to said window of time.
Claim 6
Dependent Claim
18 words
A method as recited in claim 4 further including counting said series of pulses with a counter circuit.
Claim 7
Dependent Claim
23 words
A method as recited in claim 5 further including porting a count from said counter circuit to an external tester for further calculations.
Claim 8
Independent Claim
135 words
A method for self test of a phase lock loop, the phase lock loop receiving a reference signal of a first frequency and producing an output signal of a second frequency, the second frequency being some multiple of the first frequency, the method comprising: forming a pulse of a predetermined period from the input signal of the first frequency, said predetermined period being significantly larger than the period of the second frequency produced by the phase lock loop; coupling said pulse and the output signal of the phase lock loop to an And gate thereby producing a series of pulses of the second frequency for said predetermined period of said pulse; counting said series of pulses with a counter circuit; and comparing a count of said string of pulses to an expected count of pulses.
Claim 9
Independent Claim
135 words
A method for self test of a phase lock loop, the phase lock loop receiving a reference signal of a first frequency and producing an output signal of a second frequency, the second frequency being some multiple of the first frequency, the method comprising: forming a pulse of a predetermined period from the input signal of the first frequency, said predetermined period being significantly larger than the period of the second frequency produced by the phase lock loop; coupling said pulse and the output signal of the phase lock loop to an And gate thereby producing a series of pulses of the second frequency for said predetermined period of said pulse; counting said series of pulses with a counter circuit; and comparing a count of said string of pulses to an expected count of pulses.
Claim 10
Dependent Claim
76 words
A method as recited in claim 7 wherein said forming a pulse step includes coupling the input signal of the first frequency to a divider circuit; dividing the input signal with said divider circuit thereby generating a signal of a third frequency having a period larger than the period of the input signal; coupling said signal of said third frequency to a gating circuit; and generating said pulse of said predetermined period with said gating circuit.
Claim 11
Dependent Claim
27 words
A method as recited in claim 7 further including resetting said divider circuit, said gating circuit, and said counting circuit prior to counting said series of pulses.
Claim 12
Dependent Claim
171 words
An integrated circuit with self test comprising: a phase lock loop including an input for receiving an input signal of a first frequency and an output for providing an output signal of a second frequency; a pulse circuit including an input for receiving said input signal of said first frequency and an output for providing a pulse of a predetermined period, said predetermined period being a multiple of the period of said output signal of said phase lock loop; an And gate including an input coupled to said output of said phase lock loop, an input coupled to said output of said pulse circuit, and an output, said And gate providing a series of pulses of said second frequency during said predetermined period of said pulse; and a counter circuit including an input coupled to said output of said And gate and a plurality of outputs for providing a count of said series of pulses, said count being compared with an expected count to determine accuracy of said phase lock loop.
Claim 13
Dependent Claim
171 words
An integrated circuit with self test comprising: a phase lock loop including an input for receiving an input signal of a first frequency and an output for providing an output signal of a second frequency; a pulse circuit including an input for receiving said input signal of said first frequency and an output for providing a pulse of a predetermined period, said predetermined period being a multiple of the period of said output signal of said phase lock loop; an And gate including an input coupled to said output of said phase lock loop, an input coupled to said output of said pulse circuit, and an output, said And gate providing a series of pulses of said second frequency during said predetermined period of said pulse; and a counter circuit including an input coupled to said output of said And gate and a plurality of outputs for providing a count of said series of pulses, said count being compared with an expected count to determine accuracy of said phase lock loop.
Claim 14
Dependent Claim
41 words
An integrated circuit as recited in claim 10 further including an output multiplexer circuit including a plurality of inputs coupled to said plurality of outputs of said counter circuit and an output for serial porting said count from said counter circuit.
Claim 15
Dependent Claim
71 words
An integrated circuit as recited in claim 10 wherein said pulse circuit comprises: a divider circuit including an input for receiving said reference signal and an output for providing a signal of a third frequency having a period larger than the period of the reference signal; and a gating circuit including an input receiving said signal of said third frequency and an output for providing said pulse of said predetermined period.
Claim 16
Dependent Claim
104 words
An integrated circuit as recited in claim 12 wherein said divider circuit comprises a string of series clocked D-flip flops, wherein each D-flip flop having its Qbar output coupled to its D-input, wherein the first D-flip flop of said string of series clocked D-flip flops having a clock input corresponding to said input of said divider circuit, wherein each D-flip flop other than said first D-flip flop having a D-input coupled to a preceeding D-flip flop Q output, and wherein a last D-flip flop of said string of series clocked D-flip flops having a Q output corresponding to said output of said divider circuit.
Claim 17
Dependent Claim
163 words
An integrated circuit as recited in claim 12 wherein said gating circuit comprises a shift register and a nor gate, said shift register comprises a string of series coupled D-flip flops, wherein a first D-flip flop of said string of D-flip flops includes a D-input coupled to a terminal of a power supply and a Qbar output, wherein each D-flip flop of said series coupled D-flip flops having a clock input, said clock inputs being coupled in common and corresponding to said input of said gating circuit, wherein each D-flip flop of said string of D-flip flops other than said first D-flip flop having a D-input coupled to a Q output of a preceeding D-flip flop, and wherein said nor gate includes an input coupled to said Qbar output of said first D-flip flop, an input coupled to said Q output of a last D-flip flop of said series coupled D-flip flops, and an output corresponding to said output of said gating circuit.
Claim 18
Dependent Claim
29 words
An integrated circuit as recited in claim 12 wherein said divider circuit, said gating circuit, and said counter circuit being resettable to allow retesting of said phase lock loop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-09 | 1998-07-11 | 1999-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-09 | 2002-07-11 | 2003-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-09 | 2006-07-11 | 2007-01-10 | $7700.00 | Window Closed / Lapsed |