Frequency measuring system

Claim 1

An electronic counter circuit comprising an electronic counter including a reset terminal, a clock terminal, a control terminal at which disabling and enabling signals are applied and a plurality of output terminals at which digital signals appear representing counts entered in said counter, an oscillator connected to said clock terminal, a source of counter control signals of unknown frequency, said signals each having a positive going portion and a negative going portion, said source of counter control signals coupled to said control terminal whereby one of said portions of said signal enables said counter and causes said oscillator to enter counts in said counter, the presence of said other portion of said signal at said control terminal disabling said counter, the number of counts entered in said counter by said oscillator representing the spacing between said portions of said signal and the frequency of said signal, a decoder coupled to the output terminals of said counter for receiving said binary signals and identifying the frequency relationship of said control signals, a first flip-flop having a reset terminal, a clock input terminal, a data input terminal and an output terminal, a second flip flop having a reset terminal, a clock input terminal, a data input terminal and an output terminal, said output terminal of said first flip flop being connected to said control terminal of said electronic counter, said clock terminal of said first flip flop being connected to said source of counter control signals, said output terminal of said second flip flop being connected to said data input terminal of said first flip flop, a source of command pulses coupled to said clock terminal of said second flip flop and to said reset terminal of said counter, each of said command pulses causing said counter to be reset, each command pulse operating said first and second flip flops to provide a voltage level at the output of said first flip flop which holds said counter disabled, one portion of each counter control signal coupled to said clock terminal of said first flip flop causing the voltage level on said output terminal of said first flop to change and to enable said counter whereby said oscillator can enter counts therein, the other portion of the signal coupled to said clock terminal of said first flip flop causing the voltage level on the output terminal of said first flip flop to change to a level which disables said counter and terminates the counting operation thereof.