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US5381029A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device including semiconductor layer having impurity region and method of manufacturing the same

Assignee: Mitsubishi Electric Corp
•
Filing: 1992-02-21
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Granted: 1995-01-10
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Expires: 2012-02-21
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Abstract

Abstract A semiconductor device capable of effectively preventing a dielectric breakdown of a gate oxide film without adversely affecting the characteristics of a transistor and a process of manufacturing the same are disclosed. The semiconductor device comprises a SOI film 2 whose upper angular parts are rounded off by sputter etching and a gate oxide film 3 formed on SOI film 2 with an almost uniform thickness. Therefore, electric field concentration in the upper angular parts of SOI film 2 is reduced. Furthermore, the control characteristics of the transistor are enhanced by the uniform gate oxide film 3. As a result, a dielectric breakdown of the gate oxide film is effectively prevented without adversely affecting the characteristics of the transistor. Sputter etching enabling processing at a low temperature is used, so that the upper angular parts of SOI film 2 are rounded off without adversely affecting a semiconductor element formed in the lower layer.

Inventors

  • 👤 Koji Eguchi
  • 👤 Natsuo Ajika
  • 👤 Kazuyuki Sugahara

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 03:37
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6739; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D86/00; H10D86/201; H10D88/00

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 129 words
A semiconductor device comprising: an insulating layer; a semiconductor layer formed on said insulating layer to define source/drain regions; a gate insulating film formed on said semiconductor layer with a substantially uniform thickness; and a gate electrode formed on said gate insulating film; wherein the transverse sectional form of said semiconductor layer comprises a lower trapezoid including a bottom side in contact with said insulating layer, an upper side, and lateral sides and an upper trapezoid including a bottom side which is the upper side of said lower trapezoid, an upper side, and lateral sides, and the included angles between the bottom side and the lateral sides of said lower trapezoid are larger than the included angles between the bottom side and the lateral sides of said upper trapezoid.
Claim 2
Dependent Claim 129 words
A semiconductor device comprising: an insulating layer; a semiconductor layer formed on said insulating layer to define source/drain regions; a gate insulating film formed on said semiconductor layer with a substantially uniform thickness; and a gate electrode formed on said gate insulating film; wherein the transverse sectional form of said semiconductor layer comprises a lower trapezoid including a bottom side in contact with said insulating layer, an upper side, and lateral sides and an upper trapezoid including a bottom side which is the upper side of said lower trapezoid, an upper side, and lateral sides, and the included angles between the bottom side and the lateral sides of said lower trapezoid are larger than the included angles between the bottom side and the lateral sides of said upper trapezoid.
Claim 3
Dependent Claim 88 words
A semiconductor device comprising: an insulating layer; a semiconductor layer formed on said insulating layer to define source/drain regions; a gate insulating film formed on said semiconductor layer with a substantially uniform thickness; and a gate electrode formed on said gate insulating film, the vertical profile of the entire semiconductor layer being defined by a plurality of straight line segments together forming a concave curve with respect to the surface of the insulating layer, greater than two connecting pairs of said segments intersecting each other at obtuse angles.
Claim 4
Dependent Claim 88 words
A semiconductor device comprising: an insulating layer; a semiconductor layer formed on said insulating layer to define source/drain regions; a gate insulating film formed on said semiconductor layer with a substantially uniform thickness; and a gate electrode formed on said gate insulating film, the vertical profile of the entire semiconductor layer being defined by a plurality of straight line segments together forming a concave curve with respect to the surface of the insulating layer, greater than two connecting pairs of said segments intersecting each other at obtuse angles.
Claim 5
Dependent Claim 157 words
A semiconductor device comprising: an insulating layer; a semiconductor layer of common conductivity type throughout formed on said insulating layer to define source/drain regions and having bottom surface adjacent said insulating layer and upper surface opposite to said bottom surface, the impurity concentration of said semiconductor layer at a peripheral region thereof being no greater than that at a central region thereof; a gate insulating film covering the upper surface of said semiconductor layer with a substantially uniform thickness; and a gate electrode formed on said gate insulating film; wherein the two opposed side surfaces of said semiconductor layer placed beneath said gate electrode are arcuate surfaces extending from said bottom surface to said upper surface and said side surfaces of said semiconductor layer are concave with respect to a surface of said semiconductor layer enclosed with said side surfaces, wherein the entire side surfaces of said semiconductor layer located beneath said gate electrode are arcuate surfaces.
Claim 6
Dependent Claim 157 words
A semiconductor device comprising: an insulating layer; a semiconductor layer of common conductivity type throughout formed on said insulating layer to define source/drain regions and having bottom surface adjacent said insulating layer and upper surface opposite to said bottom surface, the impurity concentration of said semiconductor layer at a peripheral region thereof being no greater than that at a central region thereof; a gate insulating film covering the upper surface of said semiconductor layer with a substantially uniform thickness; and a gate electrode formed on said gate insulating film; wherein the two opposed side surfaces of said semiconductor layer placed beneath said gate electrode are arcuate surfaces extending from said bottom surface to said upper surface and said side surfaces of said semiconductor layer are concave with respect to a surface of said semiconductor layer enclosed with said side surfaces, wherein the entire side surfaces of said semiconductor layer located beneath said gate electrode are arcuate surfaces.

References Cited (Backward Citations)

JPS58200572A Cited
JPS607729A Cited
US4546376A Cited
JPS60163457A Cited
JPS61247032A Cited
US4822751A Cited
US4753896A Cited
JPH01122167A Cited
JPH01295463A Cited
US5089870A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-01-09 1998-07-11 1999-01-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-01-09 2002-07-11 2003-01-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-01-09 2006-07-11 2007-01-10 $7700.00 Window Closed / Lapsed

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