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US5378942A
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CMOS dynamic logic structure
Assignee: National Science and Technology Council
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Filing: 1993-06-03
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Granted: 1995-01-03
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Expires: 2013-06-03
Abstract
Abstract A CMOS dynamic logic structure has a plurality of logic gates, and the logic gates includes type-1 and type-3 logic gates alternately connected with each other. Each logic gate is separated into a function unit and a driver unit. The function unit has a PMOS precharge transistor, and a logic tree block stacked with the PMOS precharge transistor. The driver unit has an NMOS evaluation transistor, and the NMOS evaluation transistor and the PMOS precharge transistor of the previous-stage logic gate is controlled by an identical clock in order not to be turned on simultaneously.
Inventors
- 👤 Chung-Yu Wu
- 👤 Kuo-Hsing Cheng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:46
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
149 words
A CMOS dynamic logic structure comprising: a plurality of logic gates connected in sequence from first to last, each logic gate including a function unit having in series a first PMOS precharge transistor, a logic tree block; and a driver unit coupled to said function unit, and having in series first, second, and third NMOS evaluation transistors, and a second PMOS precharge transistor; the gate of said second NMOS evaluation transistor being coupled to said logic tree block of said function unit, and said third NMOS evaluation transistor and said second PMOS precharge transistor being controlled by a second identical clock in order not to be turned on simultaneously; wherein, for each of said logic gates after the first, the first NMOS evaluation transistor and first PMOS precharge transistor of the previous logic gate are controlled by a first identical clock in order not to be turned on simultaneously.
Claim 2
Dependent Claim
149 words
A CMOS dynamic logic structure comprising: a plurality of logic gates connected in sequence from first to last, each logic gate including a function unit having in series a first PMOS precharge transistor, a logic tree block; and a driver unit coupled to said function unit, and having in series first, second, and third NMOS evaluation transistors, and a second PMOS precharge transistor; the gate of said second NMOS evaluation transistor being coupled to said logic tree block of said function unit, and said third NMOS evaluation transistor and said second PMOS precharge transistor being controlled by a second identical clock in order not to be turned on simultaneously; wherein, for each of said logic gates after the first, the first NMOS evaluation transistor and first PMOS precharge transistor of the previous logic gate are controlled by a first identical clock in order not to be turned on simultaneously.
Claim 3
Dependent Claim
28 words
A CMOS dynamic logic structure as claimed in claim 1, wherein each logic gate has a charge/evaluate operation phase, an evaluation operation phase, and a discharge/hold operation phase.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-02 | 1998-07-04 | 1999-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-02 | 2002-07-04 | 2003-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-02 | 2006-07-04 | 2007-01-03 | $7700.00 | Window Closed / Lapsed |