Memory transistor having increased interelectrode capacitance

Claim 2

A semiconductor memory device comprising: a semiconductor substrate; an element separating film formed on the semiconductor substrate and having separating film side surfaces; a conductive film formed on the element separating film and having conductive film side surfaces; a contact insulating film structure formed on the conductive film and having insulating film side surfaces; first side wall members formed on the separating, conductive and insulating film side surfaces of the respective element separating film, conductive film, and contact insulating film structure; a first gate insulating film structure formed on the semiconductor substrate, adjacent to the first side wall members; a first gate electrode formed on the contact insulating film structure, on the first side wall members, and on the first gate insulating film structure and having electrode side surfaces; a second gate insulating film structure formed on the first gate electrode and having second gate insulating film side surfaces; second side wall members formed on the second gate insulating film side surfaces of the second gate insulating film structure and on the electrode side surfaces of the first gate electrode; contact holes formed in the contact insulating film structure in a self alignment manner by virtue of the second side wall members, the contact holes having inner peripheral surfaces; and a second gate electrode formed on the inner peripheral surfaces of the contact holes, on the second side wall members, and on the second gate insulating film structure, the second gate electrode being connected to the conductive film.

Claim 3

The semiconductor memory device according to claim 1, wherein the conductive film is made of a material comprising one of polycrystal silicon, amorphous silicon, and a silicide.

Claim 4

The semiconductor memory device according to claim 1, wherein the first gate electrode is made of a material comprising one of polycrystal silicon, amorphous silicon, and a silicide.

Claim 5

The semiconductor memory device according to claim 1, wherein the second gate electrode is made of a material comprising one of polycrystal silicon, amorphous silicon, and a silicide.

Claim 6

A semiconductor memory device comprising: a semiconductor substrate; a first insulating film structure formed on the semiconductor substrate and having first side surfaces; a first conductive layer formed on the first insulating film structure and having first conductive layer side surfaces; a second insulating film structure formed on the first conductive layer and having second side surfaces; first side wall members formed on the first and second side surfaces of the respective first and second insulating film structures, and on the first conductive layer side surfaces of the first conductive layer; a second conductive layer formed on and connected to the semiconductor substrate, and having an end formed on the first side wall members and on the second insulating film structure, the second conductive layer having second conductive layer side surfaces; a third insulating film structure formed on the second conductive layer and having third side surfaces; second side wall members formed on the second conductive layer side surfaces of the second conductive layer and on the third side surfaces of the third insulating film structure; contact holes formed in the second insulating film structure in a self alignment manner by virtue of the second side wall members, the contact holes having inner peripheral surfaces; and a third conductive layer formed on the inner peripheral surfaces of the contact holes, on the second side wall members, and on the third insulating film structure, the third conductive layer being connected to the first conductive layer.

Claim 7

A semiconductor memory device comprising: a semiconductor substrate; a first insulating film structure formed on the semiconductor substrate and having first side surfaces; a first conductive layer formed on the first insulating film structure and having first conductive layer side surfaces; a second insulating film structure formed on the first conductive layer and having second side surfaces; first side wall members formed on the first and second side surfaces of the respective first and second insulating film structures, and on the first conductive layer side surfaces of the first conductive layer; a second conductive layer formed on and connected to the semiconductor substrate, and having an end formed on the first side wall members and on the second insulating film structure, the second conductive layer having second conductive layer side surfaces; a third insulating film structure formed on the second conductive layer and having third side surfaces; second side wall members formed on the second conductive layer side surfaces of the second conductive layer and on the third side surfaces of the third insulating film structure; contact holes formed in the second insulating film structure in a self alignment manner by virtue of the second side wall members, the contact holes having inner peripheral surfaces; and a third conductive layer formed on the inner peripheral surfaces of the contact holes, on the second side wall members, and on the third insulating film structure, the third conductive layer being connected to the first conductive layer.

Claim 8

A semiconductor memory device comprising: a semiconductor substrate; an element separating film formed on the semiconductor substrate; a conductive film formed on the element separating film; a contact insulating film structure formed on the conductive film, a first lamination comprising the element separating film, the conductive film and the contact insulating film structure having been patterned to form a first opening therethrough, the first opening exposing first side surfaces of the first lamination; first side wall members formed on the first side surfaces; a first gate insulating film structure formed on the semiconductor substrate, adjacent to the first side wall members; a first gate electrode formed on the contact insulating film structure, on the first side wall members, and on the first gate insulating film structure; a second gate insulating film structure formed on the first gate electrode, a second lamination comprising the second gate insulating film structure and the first gate electrode having been patterned to form a second opening therethrough, the second opening exposing second side surfaces of the second lamination; second side wall members formed on the second side surfaces; contact holes formed in the contact insulating film structure in a self alignment manner by virtue of the second side wall members, the contact holes exposing inner peripheral surfaces of the contact insulating film structure; and a second gate electrode formed on the inner peripheral surfaces of the contact holes, on the second side wall members, and on the second gate insulating film structure, the second gate electrode being connected to the conductive film.

Claim 9

A semiconductor memory device comprising: a semiconductor substrate; an element separating film formed on the semiconductor substrate; a conductive film formed on the element separating film; a contact insulating film structure formed on the conductive film, a first lamination comprising the element separating film, the conductive film and the contact insulating film structure having been patterned to form a first opening therethrough, the first opening exposing first side surfaces of the first lamination; first side wall members formed on the first side surfaces; a first gate insulating film structure formed on the semiconductor substrate, adjacent to the first side wall members; a first gate electrode formed on the contact insulating film structure, on the first side wall members, and on the first gate insulating film structure; a second gate insulating film structure formed on the first gate electrode, a second lamination comprising the second gate insulating film structure and the first gate electrode having been patterned to form a second opening therethrough, the second opening exposing second side surfaces of the second lamination; second side wall members formed on the second side surfaces; contact holes formed in the contact insulating film structure in a self alignment manner by virtue of the second side wall members, the contact holes exposing inner peripheral surfaces of the contact insulating film structure; and a second gate electrode formed on the inner peripheral surfaces of the contact holes, on the second side wall members, and on the second gate insulating film structure, the second gate electrode being connected to the conductive film.

Claim 10

A semiconductor memory device comprising: a semiconductor substrate; a first insulating film structure formed on the semiconductor substrate; a first conductive layer formed on the first insulating film structure; a second insulating film structure formed on the first conductive layer, a first lamination comprising the first and second insulating film structures and the first conductive layer having been patterned to form a first opening therethrough, the first opening exposing first side surfaces of the first lamination; first side wall members formed on the first side surfaces; a second conductive layer formed on and connected to the semiconductor substrate, and having an end formed on the first side wall members and on the second insulating film structure; a third insulating film structure formed on the second conductive layer, a second lamination comprising the third insulating film structure and the second conductive layer having been patterned to form a second opening therethrough, the second opening exposing second side surfaces of the second lamination; second side wall members formed on the second side surfaces; contact holes formed in the second insulating film structure in a self alignment manner by virtue of the second side wall members, the contact holes exposing inner peripheral surfaces of the contact holes; and a third conductive layer formed on the inner peripheral surfaces of the contact holes, on the second side wall members, and on the third insulating film structure, the third conductive layer being connected to the first conductive layer.

Claim 11

A semiconductor memory device comprising: a semiconductor substrate; a first insulating film structure formed on the semiconductor substrate; a first conductive layer formed on the first insulating film structure; a second insulating film structure formed on the first conductive layer, a first lamination comprising the first and second insulating film structures and the first conductive layer having been patterned to form a first opening therethrough, the first opening exposing first side surfaces of the first lamination; first side wall members formed on the first side surfaces; a second conductive layer formed on and connected to the semiconductor substrate, and having an end formed on the first side wall members and on the second insulating film structure; a third insulating film structure formed on the second conductive layer, a second lamination comprising the third insulating film structure and the second conductive layer having been patterned to form a second opening therethrough, the second opening exposing second side surfaces of the second lamination; second side wall members formed on the second side surfaces; contact holes formed in the second insulating film structure in a self alignment manner by virtue of the second side wall members, the contact holes exposing inner peripheral surfaces of the contact holes; and a third conductive layer formed on the inner peripheral surfaces of the contact holes, on the second side wall members, and on the third insulating film structure, the third conductive layer being connected to the first conductive layer.

Claim 12

A semiconductor memory device defining an MOS transistor channel length extending in a first direction between a source and a drain, the device comprising: a semiconductor substrate; an element separating film formed on the semiconductor substrate and having separating film side surfaces; a conductive film formed on the element separating film and having conductive film side surfaces; a contact insulating film structure formed on the conductive film and having insulating film side surfaces; first side wall members formed on the separating, conductive and insulating film side surfaces of the respective element separating film, conductive film, and contact insulating film structure; a first gate insulating film structure formed on the semiconductor substrate, adjacent to the first side wall members; a first gate electrode formed on the insulating film structure, on the first side wall members, and on the first gate insulating film structure and having electrode side surfaces; a second gate insulating film structure formed on the first gate electrode and having second gate insulating film side surfaces; second side wall members formed on the second gate insulating film side surfaces of the second gate insulating film structure and on the electrode side surfaces of the first gate electrode; contact holes formed in the contact insulating film structure in a self alignment manner by virtue of the second side wall members, the contact holes having inner peripheral surfaces; and a second gate electrode formed on the inner peripheral surfaces of the contact holes, on the second side wall members, and on the second gate insulating film structure, the second gate electrode being connected to the conductive film, a width of the second gate electrode extending in the first direction being substantially equal to the MOS transistor channel length.

Claim 13

A semiconductor memory device defining an MOS transistor channel length extending in a first direction between a source and a drain, the device comprising: a semiconductor substrate; an element separating film formed on the semiconductor substrate and having separating film side surfaces; a conductive film formed on the element separating film and having conductive film side surfaces; a contact insulating film structure formed on the conductive film and having insulating film side surfaces; first side wall members formed on the separating, conductive and insulating film side surfaces of the respective element separating film, conductive film, and contact insulating film structure; a first gate insulating film structure formed on the semiconductor substrate, adjacent to the first side wall members; a first gate electrode formed on the insulating film structure, on the first side wall members, and on the first gate insulating film structure and having electrode side surfaces; a second gate insulating film structure formed on the first gate electrode and having second gate insulating film side surfaces; second side wall members formed on the second gate insulating film side surfaces of the second gate insulating film structure and on the electrode side surfaces of the first gate electrode; contact holes formed in the contact insulating film structure in a self alignment manner by virtue of the second side wall members, the contact holes having inner peripheral surfaces; and a second gate electrode formed on the inner peripheral surfaces of the contact holes, on the second side wall members, and on the second gate insulating film structure, the second gate electrode being connected to the conductive film, a width of the second gate electrode extending in the first direction being substantially equal to the MOS transistor channel length.