US5377265A
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Parallel additive scrambler and descrambler
Assignee: Alcatel Lucent NV
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Filing: 1993-01-27
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Granted: 1994-12-27
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Expires: 2013-01-27
Abstract
Abstract Parallel working additive scramblers produce a predetermined pseudorandom sequence of length L in a word generator, which consists of an N-stage shift register. To obtain more than N parallel located pseudorandom sequences, the word generator is connected to a network in which, in addition to the pseudorandom sequences created by modulo-2 addition, other pseudorandom sequences are created with a different phase relation. Performing the linkage operations limits the maximum bit rate sequence that can be transmitted. The entire pseudorandom sequence is stored in a memory (S). The desired pseudorandom sequence is produced in a circular storage (RS) by means of shifting operations. The circular storage (RS) is in the form of a feedback shift register (SR) and is used as the memory (S), in which each of the outputs is connected to an input of an EXOR-gate, in which a pseudorandom sequence is modulo-2 added with a partial stream of a parallelized serial data stream. The partial streams are subsequently converted to parallel-serial form in a multiplexer. Data streams with a higher bit rate sequence are possible.
Inventors
- 👤 Heinz Wettengel
- 👤 Hartmut Borschel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 19:19
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03828; H04L25/03866; H04L25/03872
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
101 words
A parallel additive scrambler for scrambling a serial data stream converted to parallel m-bit words, where m is a positive integer, comprising: a memory (S) for storing completely a pseudorandom sequence with a length of L bits, having m parallel outputs and having means for shifting the pseudorandom sequence to form a series of phase-shifted pseudorandom sequences; and a modulo-2 adder (MOD) connected to the m parallel outputs of the memory (S), having means for adding each parallel m-bit word with one of the series of the phase-shifted pseudorandom sequences for scrambling the serial data stream with a predetermined pseudorandom sequence.
Claim 2
Dependent Claim
101 words
A parallel additive scrambler for scrambling a serial data stream converted to parallel m-bit words, where m is a positive integer, comprising: a memory (S) for storing completely a pseudorandom sequence with a length of L bits, having m parallel outputs and having means for shifting the pseudorandom sequence to form a series of phase-shifted pseudorandom sequences; and a modulo-2 adder (MOD) connected to the m parallel outputs of the memory (S), having means for adding each parallel m-bit word with one of the series of the phase-shifted pseudorandom sequences for scrambling the serial data stream with a predetermined pseudorandom sequence.
Claim 3
Dependent Claim
18 words
A scrambler as claimed in claim 1, characterized in that the memory (S) is a circulating register (RS).
Claim 4
Dependent Claim
32 words
A scrambler as claimed in claim 2, characterized in that the pseudorandom sequence consists of L bits, and that the circulating register (RS) has L locations, where L is a positive integer.
Claim 5
Dependent Claim
44 words
A scrambler as claimed in claim 3, characterized in that the word length m is greater than the length L of the pseudorandom sequence, and that the same bits of a pseudorandom sequence appear in pairs m - L outputs of the memory (S).
Claim 6
Dependent Claim
47 words
A scrambler as claimed in claim 4, characterized in that the word length is m=128 bits, that the pseudorandom sequence has a length of L=127 bits, and that the first and the last bit of a word are scrambled with the same bit of a pseudorandom sequence.
Claim 7
Dependent Claim
73 words
A scrambler as claimed in claim 2, characterized in that the pseudorandom sequence is stored in a circulating register (RS) so as to be aligned in a first direction, that the word length m of the m-bit parallel words is greater than half a length L/2 of the pseudorandom sequence, and that the modulo 2 adder (MOD) has means for shifting the pseudorandom sequence in a second direction opposite to the first direction.
Claim 8
Dependent Claim
44 words
A scrambler as claimed in claim 2, characterized in that the word length m is greater than the length L of the pseudorandom sequence, and that the same bits of a pseudorandom sequence appear in pairs m - L outputs of the memory (S).
Claim 9
Dependent Claim
20 words
A scrambler as claimed in claim 2, characterized in that the circulating register (RS) is a feedback shift register (SR).
Claim 10
Dependent Claim
72 words
A scrambler as claimed in claim 8, characterized in that the pseudorandom sequence is stored in a circulating register (RS) so as to be aligned in a first direction, that the word length m of the m-bit parallel words is greater than half length L/2 of the pseudorandom sequence, and that the modulo 2 adder (MOD) has means for shifting the pseudorandom sequence in a second direction opposite to the first direction.
Claim 11
Dependent Claim
44 words
A scrambler as claimed in claim 8, characterized in that the word length m is greater than the length L of the pseudorandom sequence, and that the same bits of a pseudorandom sequence appear in pairs m - L outputs of the memory (S).
Claim 12
Dependent Claim
32 words
A scrambler as claimed in claim 8, characterized in that the pseudorandom sequence consists of L bits, and that the circulating register (RS) has L locations, where L is a positive integer.
Claim 13
Dependent Claim
73 words
A scrambler as claimed in claim 11, characterized in that the pseudorandom sequence is stored in a circulating register (RS) so as to be aligned in a first direction, that the word Length m of the m-bit parallel words is greater than half a Length L/2 of the pseudorandom sequence, and that the modulo 2 adder (MOD) has means for shifting the pseudorandom sequence in a second direction opposite to the first direction.
Claim 14
Dependent Claim
45 words
A scrambler as claimed in claim 11, characterized in that the word length m is greater than the length L of the pseudorandom sequence, and that the same bits of a pseudorandom sequence appear in pairs at m - L outputs of the memory (S).
Claim 15
Dependent Claim
47 words
A scrambler as claimed in claim 13, characterized in that the word length is m=128 bits, that the pseudorandom sequence has a length of L=127 bits, and that the first and the last bit of a word are scrambled with the same bit of a pseudorandom sequence.
Claim 16
Dependent Claim
86 words
A scrambler as claimed in claim 11, characterized in that the pseudorandom sequence is stored in a circulating register (RS) so as to be aligned in a first direction, that an integral multiple of the m-bit parallel words is greater than an integral multiple of a Length L of the pseudorandom sequence plus more than half the Length L/2 of the pseudorandom sequence, and that the modulo 2 adder (MOD) has means for shifting the pseudorandom sequence in a second direction opposite to the first direction.
Claim 17
Dependent Claim
44 words
A scrambler as claimed in claim 1, characterized in that the word length m is greater than the length L of the pseudorandom sequence, and that the same bits of a pseudorandom sequence appear in pairs m - L outputs of the memory (S).
Claim 18
Dependent Claim
96 words
A parallel additive scrambler for scrambling a serial data stream converted to parallel words with a length m, where m is a positive integer, comprising: a memory (S) having means for storing completely a pseudorandom sequence having a length of L bits which is equal to m; and a modulo-2 adder (MOD) connected to the m parallel outputs of the memory (S), having means for inverting one part of each parallel m-bit word, and having means for regenerating another part of each parallel m-bit word, for scrambling the serial data stream with a predetermined pseudorandom sequence.
Claim 19
Dependent Claim
96 words
A parallel additive scrambler for scrambling a serial data stream converted to parallel words with a length m, where m is a positive integer, comprising: a memory (S) having means for storing completely a pseudorandom sequence having a length of L bits which is equal to m; and a modulo-2 adder (MOD) connected to the m parallel outputs of the memory (S), having means for inverting one part of each parallel m-bit word, and having means for regenerating another part of each parallel m-bit word, for scrambling the serial data stream with a predetermined pseudorandom sequence.
Claim 20
Dependent Claim
101 words
A parallel additive descrambler for descrambling a serial data stream converted to parallel m-bit words, where m is a positive integer, comprising: a memory (S) for storing completely a pseudorandom sequence with a length of L bits, having m parallel outputs and having means for shifting the pseudorandom sequence to form a series of phase-shifted pseudorandom sequences; and a modulo-2 adder (MOD) connected to the m parallel outputs of the memory (S), having means for adding each parallel m-bit word with one of the series of the phase-shifted pseudorandom sequences for descrambling the serial data stream with a predetermined pseudorandom sequence.
Claim 21
Dependent Claim
101 words
A parallel additive descrambler for descrambling a serial data stream converted to parallel m-bit words, where m is a positive integer, comprising: a memory (S) for storing completely a pseudorandom sequence with a length of L bits, having m parallel outputs and having means for shifting the pseudorandom sequence to form a series of phase-shifted pseudorandom sequences; and a modulo-2 adder (MOD) connected to the m parallel outputs of the memory (S), having means for adding each parallel m-bit word with one of the series of the phase-shifted pseudorandom sequences for descrambling the serial data stream with a predetermined pseudorandom sequence.
Claim 22
Dependent Claim
92 words
A parallel additive descrambler for descrambling a serial data stream converted to parallel m-bit words, where m is a positive integer, a memory (S) having means for storing completely a pseudorandom sequence having a length of L bits which is equal to m; and a modulo-2 adder (MOD) connected to the m parallel outputs of the memory (S), having means for inverting one part of each parallel m-bit word, and having means for regenerating another part of each parallel m-bit word, for descrambling the serial data stream with a predetermined pseudorandom sequence.
Claim 23
Dependent Claim
92 words
A parallel additive descrambler for descrambling a serial data stream converted to parallel m-bit words, where m is a positive integer, a memory (S) having means for storing completely a pseudorandom sequence having a length of L bits which is equal to m; and a modulo-2 adder (MOD) connected to the m parallel outputs of the memory (S), having means for inverting one part of each parallel m-bit word, and having means for regenerating another part of each parallel m-bit word, for descrambling the serial data stream with a predetermined pseudorandom sequence.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-26 | 1998-06-27 | 1998-12-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-26 | 2002-06-27 | 2002-12-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-26 | 2006-06-27 | 2006-12-27 | $7700.00 | Window Closed / Lapsed |