Pseudo random pattern generating device

Claim 2

A pseudo random pattern generating device comprising: pattern memory means wherein there are stored at 2 n-m (where n is an integer equal to or greater than 3 and m is a positive integer smaller than n) addresses 2 n-m subpatterns of at least (2 m+1 -1) bits in length, each of said subpatterns being composed of one of 2 n-m split patterns into which a pseudo random pattern, which recurs on a cycle of (2"-1) bits, is split at intervals of 2" bits, starting at the beginning of said pseudo random pattern, and a continuation pattern of a predetermined number of bits subsequent to said each split pattern in said recurring pseudo random pattern; a 2 n-m counter which counts a clock and sequentially outputs the count values as address signals; readout means which is supplied with said address signals one after another and reads out said subpatterns stored in said pattern memory means at addresses corresponding to said address signals, in synchronism with said clock; shift means for selectively outputting a pattern composed of contiguous 2m bits in each of said subpatterns read out by said readout means from said addresses while shifting said 2m-bit pattern one bit position upon each readout of said 2 n-m subpatterns; latch means for latching said 2 m -bit pattern output from said shift means; and parallel-serial converting means which is supplied with said 2 m- bit pattern in parallel form from said latch means and outputs it as a serial pattern.

Claim 3

The device of claim 1, wherein said continuation pattern composed of a predetermined number of bits, added to each of said 2m.bit subpatterns is a 2m-bit pattern and said subpatterns stored in said pattern memory means at respective addresses thereof are each stored as one word of 2 m+1 bits in length.

Claim 4

The device of claim 2, wherein said pattern memory means is a read/write memory and said shift means includes shift register means to which each of said 2 m+1 -bit subpatterns read out of the respective addresses of said pattern memory means is applied in parallel and which circular-shifts said subpattern one bit position, and write means for said circular-shifted subpattern into said pattern memory means at the address from which said subpattern was read out.

Claim 5

The device of claim 3, wherein said shift register means includes a (2 m+1 +1)-stage shift register; each of said 2 m+1 subpatterns is applied in parallel to second to (2 m+1 + 1)th stages of said shift register from said pattern memory means; a pattern composed of 2m bits from the first to (2 m )th stages of said shift register is provided in parallel to said latch means; the output of the second stage of said shift register is connected to the input of the (2 m+1 +1)th stage thereof; said shift register responds to said clock to shift its contents toward said first stage thereof and, at the same time, circular-shifts the content of said second stage to said (2 m+1 +1)th stage.

Claim 6

The device of claim 4, wherein said write means includes: a 2 n counter for counting said clock; adjust pulse generating means which upon each counting of 2" shots of said clock by said 2 n counter generates a shift adjust pulse and applies it as a shift signal to said shift register; and changeover switch means which upon each counting of 2 n shots of said clock by said 2" counter exchanges the bit positions of first to 2 m th bits and (2 m +1)th to (2 m+1 )th bits of each of said subpatterns read out of said pattern memory means and then provides them to said shift register.

Claim 7

The device of claim 2, wherein said continuation pattern of a predetermined number of bits, added to each 2 m- bit subpattern, is a (2 m+1 -l)-bit pattern and said subpattern stored at each address of said pattern memory means is stored as a word of (2 m+1 -1) bits in length.

Claim 8

The device of claim 6, wherein said shift means includes: multiplexer means which is supplied with a (2 m+1 -1)-bit read output of said pattern memory means and selectively supplies said latch means with desired contiguous 2 m bits of said applied (2 m+1 -1) bits, and shift control means whereby said contiguous 2 m bits selected by said multiplexer means are shifted one bit position upon each counting of 2 n-m shots of said clock.

Claim 9

The device of claim 7, wherein said shift control means includes address adjust means for setting said 2 n-m counter to a predetermined value upon each counting of 2 n shots of said clock.

Claim 10

A pseudo random pattern generating device comprising: memory wherein there are respectively stored, as one word, 2 n /2 m = 2 n-m (n is an integer equal to or greater than 3 and m is a positive integer smaller than n) subpatterns of 2 m+1 bits in length, each of said subpatterns being composed of one of split patterns into which a pseudo random pattern, which recurs on a cycle of (2 n -1) bits, is split at intervals of 2m bits and a continuation pattern of 2m bits subsequent to said each split pattern; a 2 n-m address counter for counting a clock and providing the count value as an address signal to said memory; a shift register into which a pattern read out of said memory is input in parallel for each clock; means whereby said pattern parallel-input into said shift register is shifted one bit position; means for writing said shifted pattern into said memory; a latch wherein a pattern composed of 2m bits at one end of said pattern in said shift register is latched by said clock after writing said shifted pattern into said memory; a parallel-serial converter for converting said latched pattern into a serial pattern; a 2 m counter for counting said clock; means for switching output and input patterns of said memory by the output of said 2 n counter every 2 m bits; and means responsive to the output of said 2 n counter to increment said address counter by one, input in parallel the read-out pattern from said memory into said shift register, shifting said parallel-input pattern one bit position, and cause said write means to write said shifted pattern.

Claim 11

A pseudo random pattern generating device comprising: memory wherein there are respectively stored, as one word, 2 n /2 m = 2 n-m (n is an integer equal to or greater than 3 and m is a positive integer smaller than n) subpatterns of 2 m+1 bits in length, each of said subpatterns being composed of one of split patterns into which a pseudo random pattern, which recurs on a cycle of (2 n -1) bits, is split at intervals of 2m bits and a continuation pattern of 2m bits subsequent to said each split pattern; a 2 n-m address counter for counting a clock and providing the count value as an address signal to said memory; a shift register into which a pattern read out of said memory is input in parallel for each clock; means whereby said pattern parallel-input into said shift register is shifted one bit position; means for writing said shifted pattern into said memory; a latch wherein a pattern composed of 2m bits at one end of said pattern in said shift register is latched by said clock after writing said shifted pattern into said memory; a parallel-serial converter for converting said latched pattern into a serial pattern; a 2 m counter for counting said clock; means for switching output and input patterns of said memory by the output of said 2 n counter every 2 m bits; and means responsive to the output of said 2 n counter to increment said address counter by one, input in parallel the read-out pattern from said memory into said shift register, shifting said parallel-input pattern one bit position, and cause said write means to write said shifted pattern.

Claim 12

A pseudo random pattern generating device comprising: memory wherein there are respectively stored, as one word, 2 n /2 m = 2 n-m (where n is an integer equal to or greater than 3 and m is a positive integer smaller than n) subpatterns of (2 m+1 -1) bits in length, each of said subpatterns being composed of one of split patterns into which a pseudo random pattern, which recurs on a cycle of (2 n-1 ) bits, is split at intervals of 2m bits and a continuation pattern of (2 m-1 -1) bits subsequent to said each split pattern; a 2 2-m counter for counting a clock and providing the count value as an address signal to said memory; a 2m counter for counting a carry of said 2 n-m counter; a multiplexer which is supplied with the count value of said 2 m counter, as a control input, and outputs, in accordance with said control input, one of 2m combinations of patterns of sequentially contiguous 2m bits in a (2 m + 2 m - 1 )-bit pattern read out of said memory; a latch into which the output of said multiplexer is input upon each generation of said clock; a parallel-serial converter for converting the output of said latch into a serial pattern; and means for incrementing said 2 n-m counter by one upon each generation of the output of said 2 m counter.

Claim 13

A pseudo random pattern generating device comprising: memory wherein there are respectively stored, as one word, 2 n /2 m = 2 n-m (where n is an integer equal to or greater than 3 and m is a positive integer smaller than n) subpatterns of (2 m+1 -1) bits in length, each of said subpatterns being composed of one of split patterns into which a pseudo random pattern, which recurs on a cycle of (2 n-1 ) bits, is split at intervals of 2m bits and a continuation pattern of (2 m-1 -1) bits subsequent to said each split pattern; a 2 2-m counter for counting a clock and providing the count value as an address signal to said memory; a 2m counter for counting a carry of said 2 n-m counter; a multiplexer which is supplied with the count value of said 2 m counter, as a control input, and outputs, in accordance with said control input, one of 2m combinations of patterns of sequentially contiguous 2m bits in a (2 m + 2 m - 1 )-bit pattern read out of said memory; a latch into which the output of said multiplexer is input upon each generation of said clock; a parallel-serial converter for converting the output of said latch into a serial pattern; and means for incrementing said 2 n-m counter by one upon each generation of the output of said 2 m counter.