US5377154A — Multiple serial-access memory

Claim 1

Independent Claim 81 words

A serial access memory fabricated as a single integrated circuit, comprising: a plurality of memory cell arrays for storing data; a like plurality of serial output ports coupled for serial output of data from respective memory cell arrays; at least one serial input port coupled for input of serial data to one of said memory cell arrays; and at least one transfer circuit coupled to transfer data from one of said memory cell arrays to another of said memory cell arrays.

Claim 2

Dependent Claim 81 words

A serial access memory fabricated as a single integrated circuit, comprising: a plurality of memory cell arrays for storing data; a like plurality of serial output ports coupled for serial output of data from respective memory cell arrays; at least one serial input port coupled for input of serial data to one of said memory cell arrays; and at least one transfer circuit coupled to transfer data from one of said memory cell arrays to another of said memory cell arrays.

Claim 3

Dependent Claim 14 words

The memory of claim 1, wherein said transfer circuit transfers data in parallel form.

Claim 4

Dependent Claim 77 words

The memory of claim 1, wherein for each serial output port among said plurality of serial output ports, said memory receives a corresponding read enable signal to which said serial output port responds by: outputting successive serial data while said read enable signal is active; and continuing to output a last data of the successive serial data that is output before said enable signal is changed from active to inactive, while said read enable signal is inactive.

Claim 5

Dependent Claim 58 words

The memory of claim 1, wherein for each serial output port among said plurality of serial output ports, said memory receives a corresponding output enable signal to which said serial output port responds by: outputting successive serial data while said output enable signal is active; and going to a high-impedance state while said output enable signal is inactive.

Claim 6

Dependent Claim 108 words

The memory of claim 1, wherein for each serial output port among said plurality of serial output ports, said memory receives a corresponding read enable signal and a corresponding output enable signal, to which said serial output port responds by: outputting successive serial data while said read enable signal and said output enable signal are both active; continuing to output a last data of the successive serial data that is output before said enable signal is changed from active to inactive, while said read enable signal is inactive and said output enable signal is active; and going to a high-impedance state while said output enable signal is inactive.

Claim 7

Dependent Claim 41 words

The memory of claim 1, wherein said memory receives a chip enable signal and responds by disabling serial input at said serial input port and serial output at all of said serial output ports while said chip enable signal is inactive.

Claim 8

Dependent Claim 25 words

The memory of claim 1, wherein said memory receives a clock signal and receives data at said input port in synchronization with said clock signal.

Claim 9

Dependent Claim 22 words

The memory of claim 7, wherein said memory outputs data at all of said output ports in synchronization with said clock signal.

Claim 10

Dependent Claim 28 words

The memory of claim 1, wherein said memory receives a read clock signal and outputs data from all of said output ports in synchronization with read clock signal.

Claim 11

Dependent Claim 44 words

The memory of claim 1, wherein said memory receives a plurality of read clock signals comprising, for each of said output ports, a corresponding read clock signal, and outputs data from each of said output ports in synchronization with the corresponding read clock signal.

Claim 12

Dependent Claim 137 words

A serial access memory fabricated as a single integrated circuit, comprising: a plurality of memory cell arrays for storing data, said memory cell arrays being arranged in a series from a first memory cell array to a last memory cell array, each memory cell array except said last memory cell array being followed by a respective next memory cell array in said series; a like plurality of serial output ports coupled for serial output of data transferred out of corresponding memory cell arrays; a serial input port coupled to input serial data for transfer into said first memory cell array; and for each memory cell array except the last memory cell array in said series, a corresponding transfer circuit coupled to transfer data from that memory cell array to the next memory cell array in said series.

Claim 13

Dependent Claim 137 words

A serial access memory fabricated as a single integrated circuit, comprising: a plurality of memory cell arrays for storing data, said memory cell arrays being arranged in a series from a first memory cell array to a last memory cell array, each memory cell array except said last memory cell array being followed by a respective next memory cell array in said series; a like plurality of serial output ports coupled for serial output of data transferred out of corresponding memory cell arrays; a serial input port coupled to input serial data for transfer into said first memory cell array; and for each memory cell array except the last memory cell array in said series, a corresponding transfer circuit coupled to transfer data from that memory cell array to the next memory cell array in said series.

Claim 14

Dependent Claim 106 words

The memory of claim 11, wherein said memory receives, corresponding to said plurality of memory cell arrays, a like plurality of row address strobe signals and a like plurality of read transfer signals and a like plurality of read transfer signals so that each row address signal has a corresponding read transfer signal and a corresponding memory cell array, and when a row address strobe signal is active said memory responds by: transferring data into the corresponding memory cell array if the corresponding read transfer signal is inactive; and transferring data out of the corresponding memory cell array if the corresponding read transfer signal is active.

Claim 15

Dependent Claim 89 words

The memory of claim 11, wherein said memory receives a row address strobe signal and, corresponding to said plurality of memory cell arrays, a like plurality of read transfer signals, so that each memory cell array has a corresponding read transfer signal, and when said row address strobe signal is active said memory responds by: transferring data into each memory cell array for which the corresponding read transfer signal is inactive; and transferring data out of each memory cell array for which the corresponding read transfer signal is active.

Claim 16

Dependent Claim 30 words

The memory of claim 11, wherein each of said memory cell arrays comprises a matrix of memory cells and each memory cell is identified by an X-address and a Y-address.

Claim 17

Dependent Claim 41 words

The memory of claim 14, further comprising, corresponding to said plurality of memory cell arrays, a like plurality of X-addressing circuits, each X-addressing circuit being coupled to a corresponding memory cell array and selecting memory cells therein according to their X-addresses.

Claim 18

Dependent Claim 42 words

The memory of claim 15, wherein each transfer circuit simultaneously transfers data obtained from all memory cells selected by the X-addressing circuit of the corresponding memory cell array to memory cells selected by the X-addressing circuit of the next memory cell array.

Claim 19

Dependent Claim 89 words

The memory of claim 15, further comprising, for said first memory cell array: an input register having storage elements corresponding to Y-addresses of said first memory cell array, coupled to receive data in serial form from said serial input port, temporarily store the data received, and provide the same data in parallel form to memory cells selected by the X-addressing circuit of said first memory cell array; and a write Y-addressing circuit for receiving Y-address signals and selecting corresponding storage elements in said input register for storing said data.

Claim 20

Dependent Claim 64 words

The memory of claim 17, further comprising, corresponding to said plurality of memory cell arrays, a like plurality of output registers, each output register being coupled to a corresponding memory cell array, for receiving data in parallel form from memory cells selected by said X-addressing circuits, temporarily storing the data received, and providing the same data in serial form to corresponding serial output ports.

Claim 21

Dependent Claim 61 words

The memory of claim 18, wherein each memory cell array has pair of complementary bit lines, each pair of complementary bit lines being identified by a Y-address and coupled to memory cells having the same Y-address, and each said output register separately comprises a plurality of flip-flops coupled to said pairs of complementary bit lines in the corresponding memory cell array.

Claim 22

Dependent Claim 73 words

The memory of claim 19, wherein for each memory cell array except that the last memory cell array in said series, the corresponding transfer circuit comprises pairs of transistors coupling said flip-flops in the corresponding output register to corresponding pairs of bit lines in the next memory cell array, thereby enabling data to be transferred from said memory cell array to said corresponding output register and to the next memory cell array simultaneously.

Claim 23

Dependent Claim 47 words

The memory of claim 18, further comprising, corresponding to said plurality of memory cell arrays, a like plurality of read Y-addressing circuits, each read Y-addressing circuit being coupled to a corresponding output register for selection of data stored therein to be provided to corresponding serial output ports.

Claim 24

Dependent Claim 22 words

The memory of claim 21, further comprising a write Y-address generator for generating Y-addresses and providing same to said write Y-addressing circuit.

Claim 25

Dependent Claim 25 words

The memory of claim 22, wherein said write Y-address generator also supplies Y-addresses to the read Y-addressing circuits of all of said memory cell arrays.

Claim 26

Dependent Claim 14 words

The memory of claim 22, wherein said write Y-address generator latches external Y-address signals.

Claim 27

Dependent Claim 14 words

The memory of claim 22, wherein said write Y-address generator comprises a resettable counter.

Claim 28

Dependent Claim 28 words

The memory of claim 25, wherein the resettable counter of said write Y-address generator is reset to zero when data are transferred into said first memory cell array.

Claim 29

Dependent Claim 30 words

The memory of claim 22, further comprising a read Y-address generator for generating a Y-addresses and providing same to the read Y-addressing circuits of all of said memory cell arrays.

Claim 30

Dependent Claim 14 words

The memory of claim 27, wherein said read Y-address generator latches external Y-address signals.

Claim 31

Dependent Claim 14 words

The memory of claim 27 wherein said read Y-address generator comprises a resettable counter.

Claim 32

Dependent Claim 29 words

The memory of claim 29, wherein the resettable counter of said read Y-address generator is reset to zero when data are transferred out of said first memory cell array.

Claim 33

Dependent Claim 38 words

The memory of claim 21, further comprising, corresponding to said plurality of memory cell arrays, a like plurality of read Y-address generators for generating Y-addresses and providing same to the read Y-addressing circuits of respective memory cell arrays.

Claim 34

Dependent Claim 17 words

The memory of claim 31, wherein each of said read Y-address generators separately latches external Y-address signals.

Claim 35

Dependent Claim 17 words

The memory of claim 31, wherein each of said read Y-address generators separately comprises a resettable counter.

Claim 36

Dependent Claim 31 words

The memory of claim 33, wherein the resettable counter of each of said read Y-address generators is reset to zero when data are transferred out of the corresponding memory cell array.

Claim 37

Dependent Claim 29 words

The memory of claim 15, further comprising an X-address generator for latching external X-address signals and providing same to the X-addressing circuits of all of said memory cell arrays.

Claim 38

Dependent Claim 58 words

The memory of claim 15, further comprising, corresponding to the plurality of memory cell arrays, a like plurality of X-address generators arranged in a series from a first X-address generator to a last X-address generator, wherein each X-address generator has a corresponding memory cell array and provides X-addresses to the X-addressing circuit of the corresponding memory cell array.

Claim 39

Dependent Claim 16 words

The memory of claim 36, wherein each of said X-address generators separately latches external X-address signals.

Claim 40

Dependent Claim 31 words

The memory of claim 36, wherein each of said X-address generators separately comprises a write counter that generates X-addresses for use when data are transferred into the corresponding memory cell array.

Claim 41

Dependent Claim 19 words

The memory of claim 38, wherein said memory receives a plurality of initializing signals for initializing said X-address generators.

Claim 42

Dependent Claim 52 words

The memory of claim 39, wherein said first X-address generator also comprises a delay line for temporarily storing the X-addresses generated by the write counter of said first X-address generator, thereby permitting initialization of the write counter in said first X-address generator to precede input of corresponding data at said input port.

Claim 43

Dependent Claim 27 words

The memory of claim 39, wherein the write counter in said fist X-address generator is incremented when time data are transferred into said first memory cell array.

Claim 44

Dependent Claim 37 words

The memory of claim 39 wherein, when data are transferred out of each memory cell array except the last memory cell array, the write counter in the X-address generator of the next memory cell array is incremented.

Claim 45

Dependent Claim 19 words

The memory of claim 39, wherein the write counter in each of said X-address generators is initialized to zero.

Claim 46

Dependent Claim 23 words

The memory of claim 39, wherein the write counter in each of said X-address generators is initialized according to an external X-address signal.

Claim 47

Dependent Claim 32 words

The memory of claim 39, wherein said first X-address generator also comprises a read counter that generates X-addresses for use when data are transferred out of all of said memory cell arrays.

Claim 48

Dependent Claim 28 words

The memory of claim 45, wherein the read counter of said first X-address generator is incremented each time data are transferred out of said first memory cell array.

Claim 49

Dependent Claim 48 words

The memory of claim 45, wherein said plurality of initializing signals comprises a separate initializing signal for initializing the write counter in each of said X-address generators the read counter in said first X-address generator being initialized when the write counter in the next X-address generator is initialized.

Claim 50

Dependent Claim 18 words

The memory of claim 47, wherein the read counter in said first X-address generator is initialized to zero.

Claim 51

Dependent Claim 22 words

The memory of claim 47, wherein the read counter in said first X-address generator is initialized according to an external X-address signal.

Claim 52

Dependent Claim 32 words

The memory of claim 39, wherein each of said X-address generators separately comprises a read-address counter that generates X-addresses for use when data are transferred out of the corresponding memory cell array.

Claim 53

Dependent Claim 30 words

The memory of claim 50, wherein the read X-address counter in each of said X-address generators is incremented each time data are transferred out of the corresponding memory cell array.

Claim 54

Dependent Claim 19 words

The memory of claim 50, wherein the read counter in each of said address generators is initialized to zero.

Claim 55

Dependent Claim 23 words

The memory of claim 50, wherein the read counter in each of said X-address generators is initialized according to an external X-address signal.

Claim 56

Dependent Claim 43 words

The memory of claim 50, wherein the write counter in each of said X-address generators except the first X-address generator is initialized to zero, and the read counter in each of said X-address generators except the last X-address generator is initialized to zero.

Claim 57

Dependent Claim 73 words

The memory of claim 50, wherein said plurality of initializing signals comprises: a first initializing signal for initializing the write counter of said first X-address generator; a last initializing signal for initializing the read counter of said last X-address generator; and for each X-address generator except the last X-address generator, a corresponding initializing signal for initializing both the read counter in said X-address generator and the write counter in the next X-address generator.

Claim 58

Independent Claim 132 words

A method of storing data in an integrated circuit having a series of at least two memory cell arrays and a corresponding series of at least two output registers, and reading the stored data, comprising the steps of: (a) writing serial data into an input register in said integrated circuit; (b) transferring data in parallel from said input register to a first memory cell array in said series of memory cell arrays; (c) transferring data in parallel between each pair of adjacent memory cell arrays in said series of memory cell arrays, starting from said first memory cell array; (d) transferring data in parallel from each memory cell array in said series to a corresponding output register in said series of output registers; and (e) reading data serially from said output registers.

Claim 59

Independent Claim 132 words

A method of storing data in an integrated circuit having a series of at least two memory cell arrays and a corresponding series of at least two output registers, and reading the stored data, comprising the steps of: (a) writing serial data into an input register in said integrated circuit; (b) transferring data in parallel from said input register to a first memory cell array in said series of memory cell arrays; (c) transferring data in parallel between each pair of adjacent memory cell arrays in said series of memory cell arrays, starting from said first memory cell array; (d) transferring data in parallel from each memory cell array in said series to a corresponding output register in said series of output registers; and (e) reading data serially from said output registers.

Claim 60

Dependent Claim 25 words

The method of claim 56, wherein said steps (c) and (d) are performed simultaneously, with transfer of identical data in both steps (c) and (d).

Claim 61

Dependent Claim 14 words

The method of claim 56, wherein said steps (a) and (e) are performed simultaneously.

Claim 62

Dependent Claim 37 words

The method of claim 56, comprising the further step of: (f) generating, by means of counters in said integrated circuit, addresses in said memory cell arrays for use in transferring data in said steps (c) and (d).

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1997-12-26	1998-06-27	1998-12-27	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2001-12-26	2002-06-27	2002-12-27	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2005-12-26	2006-06-27	2006-12-27	$7700.00	Window Closed / Lapsed

Multiple serial-access memory

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