Digital-to-analog and analog-to-digital converters using electrically programmable floating gate transistors

Claim 2

A digital-to-analog converter, comprising: (A) a first electrically programmable floating gate transistor having a drain, a source, a control gate, and a floating gate, wherein the first transistor is electrically programmed by a programming and erasure circuit to have a first electrically programmable threshold voltage; (B) a second electrically programmable floating gate transistor having a drain, a source, a control gate, and a floating gate, wherein the second transistor is electrically programmed by the programming and erasure circuit to have a second electrically programmable threshold voltage, wherein the first programmable threshold voltage has a voltage level that is different from that of the second programmable threshold voltage, wherein the control gate of the first and second transistors is coupled to an output node, wherein the output node is coupled to a first voltage source via load circuitry, wherein the source of the first and second transistors is coupled to a second voltage source; (C) circuitry coupled to receive a digital input signal for selectively coupling the drain of one of the first and second transistors to the output node in response to the digital signal, wherein (1) when the drain of the first transistor is coupled to the output node, the output node is set at the first programmable threshold voltage, and (2) when the drain of the second transistor is coupled to the output node, the output node is set at the second programmable threshold voltage such that the digital input signal is converted into an analog voltage.

Claim 3

The digital-to-analog converter of claim 1, wherein the circuitry further comprises (i) first switching circuitry for coupling the drain of the first transistor to the output node in response to a first control signal; (ii) second switching circuitry for coupling the drain of the second transistor to the output node in response to a second control signal; (iii) input circuitry coupled to receive the digital input signal for decoding the digital input signal to generate one of the first and second control signals at a time, wherein the input circuitry couples the first control signal to the first switching circuitry and the second control signal to the second switching circuitry.

Claim 4

The digital-to-analog converter of claim 2, further comprising a plurality of electrically programmable floating gate transistors, including the first and second transistors, and a plurality of switching circuitry, including the first and second switching circuitry, each being coupled to the drain of one of the plurality of electrically programmable floating gate transistors, wherein each of the plurality of electrically programmable floating gate transistors has a programmable threshold voltage.

Claim 5

The digital-to-analog converter of claim 3, wherein the input circuitry generates a plurality of control signals, each for one of the plurality of switching circuitry, wherein the input circuitry causes only one of the plurality of switching circuitry to couple the drain of the respective one of the plurality of electrically programmable floating gate transistors to the output node at a time.

Claim 6

The digital-to-analog converter of claim 2, wherein the input circuitry further comprises a decoder.

Claim 7

The digital-to-analog converter of claim 1, wherein the programming and erasure circuit can also erase the first and second electrically programmable threshold voltages of the respective first and second transistors.

Claim 8

An analog-to-digital converter, comprising: (A) a first electrically programmable floating gate transistor having a drain, a source, a control gate, and a floating gate, wherein the first transistor is electrically programmed by a programming and erasure circuit to have a first electrically programmable threshold voltage, wherein the drain of the first transistor is coupled to a first output node, wherein the first output node is coupled to a first voltage source via first load circuitry; (B) a second electrically programmable floating gate transistor having a drain, a source, a control gate, and a floating gate, wherein the second transistor is electrically programmed by the programming and erasure circuit to have a second electrically programmable threshold voltage, wherein the drain of the second transistor is coupled to a second output node, wherein the first programmable threshold voltage has a voltage level that is different from that of the second programmable threshold voltage, wherein the second output node is coupled to the first voltage source via second load circuitry, wherein the source of the first and second transistors is coupled to a second voltage source, wherein the control gate of the first and second transistors is coupled to receive an input analog voltage, wherein when the input analog voltage is greater than or equal to the first programmable threshold voltage, the first transistor is conducting and the first output node generates a first signal, wherein when the input analog voltage is greater than or equal to the second programmable threshold voltage, the second transistor is conducting and the second output node generates a second signal; (C) output circuitry coupled to the first and second output nodes for encoding the first and second signals into a digital output signal such that the input analog voltage is converted into the digital output signal.

Claim 9

An analog-to-digital converter, comprising: (A) a first electrically programmable floating gate transistor having a drain, a source, a control gate, and a floating gate, wherein the first transistor is electrically programmed by a programming and erasure circuit to have a first electrically programmable threshold voltage, wherein the drain of the first transistor is coupled to a first output node, wherein the first output node is coupled to a first voltage source via first load circuitry; (B) a second electrically programmable floating gate transistor having a drain, a source, a control gate, and a floating gate, wherein the second transistor is electrically programmed by the programming and erasure circuit to have a second electrically programmable threshold voltage, wherein the drain of the second transistor is coupled to a second output node, wherein the first programmable threshold voltage has a voltage level that is different from that of the second programmable threshold voltage, wherein the second output node is coupled to the first voltage source via second load circuitry, wherein the source of the first and second transistors is coupled to a second voltage source, wherein the control gate of the first and second transistors is coupled to receive an input analog voltage, wherein when the input analog voltage is greater than or equal to the first programmable threshold voltage, the first transistor is conducting and the first output node generates a first signal, wherein when the input analog voltage is greater than or equal to the second programmable threshold voltage, the second transistor is conducting and the second output node generates a second signal; (C) output circuitry coupled to the first and second output nodes for encoding the first and second signals into a digital output signal such that the input analog voltage is converted into the digital output signal.

Claim 10

The analog-to-digital converter of claim 7, wherein the digital output signal has a first digital value when the first output node generates the first signal, wherein the digital output signal has a second digital value when the second output node generates the second signal.

Claim 11

The analog-to-digital converter of claim 7, wherein the programming and erasure circuit can also erase the first and second electrically programmable threshold voltages of the respective first and second transistors.

Claim 12

The analog-to-digital converter of claim 7, further comprising a plurality of electrically programmable floating gate transistors, including the first and second transistors, each having a floating gate, a control gate coupled to the input analog voltage, a source coupled to the second voltage source, a drain coupled to one of a plurality of output nodes, wherein each of the plurality of output nodes is coupled to the first voltage via one of a plurality of load circuitry, wherein each of the plurality of electrically programmable floating gate transistors has a programmable threshold voltage.

Claim 13

The analog-to-digital converter of claim 10, wherein each of the plurality of output nodes generates a signal to the output circuitry when its respective one of the plurality of electrically programmable floating gate transistors is caused to be conducting, wherein the output circuitry generates the digital output signal in accordance with one of the plurality of electrically programmable floating gate transistors that has a highest threshold voltage among a number of the plurality of electrically programmable floating gate transistors that are conducting.

Claim 14

The analog-to-digital converter of claim 7, wherein the output circuitry further comprises a decoder.