US5376435A
Expired / Lapsed
US
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Microelectronic interlayer dielectric structure
Assignee: Seiko Epson Corp
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Filing: 1993-07-16
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Granted: 1994-12-27
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Expires: 2013-07-16
Abstract
Abstract An interlayer dielectric structure for microelectronic devices having multiple conducting layers provides a planarized surface for deposition of subsequent layers and further prevents cracking of spin-on-glass by limiting spin-on-glass thickness to about 0.4 μm or less. A first dielectric layer is formed over a first conducting layer by means of reacting Si(OC 2 H 5 ) 4 and O 2 at approximately 9 torr between 370° C. to 400° C., and a second dielectric layer is formed over the first dielectric layer by a method different than that used to form the first dielectric layer. After etching back the second dielectric layer, a spin-on-glass layer is formed. Spin-on-glass layer is etched back to provide a planar surface and a third dielectric-layer is formed over the spin-on-glass layer. The resulting surface is ready for contact hole formation, deposition and patterning of subsequent conductive and insulating layers.
Inventors
- 👤 Yukio Morozumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:42
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; H10W20/092; Y; Y10; Y10T; Y10T428/00; Y10T428/24; Y10T428/24802; Y10T428/24917; Y10T428/24926
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
131 words
A dielectric structure for semiconductor devices having multiple conductive layers comprising: a) at least one first conductive line disposed on said semiconductor device; b) a first insulating layer formed over said at least one conductive line and said semiconductor device, such that it has compression stress and a non-planar surface; c) a second insulating layer formed over said first insulating layer such that said second insulating layer has tensile stress and the combination of first and second insulating layers has a non-planar surface; d) a plurality of spin-on-glass regions formed over said second insulating layer such that the combination of said spin-on-glass regions and said second insulator regions has a substantially planar surface; and e) a third insulating layer formed over said first insulator, said second insulator and said spin-on-glass regions.
Claim 2
Dependent Claim
131 words
A dielectric structure for semiconductor devices having multiple conductive layers comprising: a) at least one first conductive line disposed on said semiconductor device; b) a first insulating layer formed over said at least one conductive line and said semiconductor device, such that it has compression stress and a non-planar surface; c) a second insulating layer formed over said first insulating layer such that said second insulating layer has tensile stress and the combination of first and second insulating layers has a non-planar surface; d) a plurality of spin-on-glass regions formed over said second insulating layer such that the combination of said spin-on-glass regions and said second insulator regions has a substantially planar surface; and e) a third insulating layer formed over said first insulator, said second insulator and said spin-on-glass regions.
Claim 3
Dependent Claim
29 words
The dielectric structure of claim 1, further comprising at least one window formed in said dielectric structure such that a corresponding portion of said first conductive line is exposed.
Claim 4
Dependent Claim
19 words
The dielectric structure of claim 1, further comprising at least one second conductive line formed over said dielectric structure.
Claim 5
Dependent Claim
23 words
The dielectric structure of claim 1, wherein said first conductive line is made of an Al-Cu alloy and is approximately 0.6 μm thick.
Claim 6
Dependent Claim
18 words
The dielectric structure of claim 1, wherein said first, second and third insulating layers are silicon oxide films.
Claim 7
Dependent Claim
17 words
The dielectric structure of claim 1, wherein said spin-on-glass regions are less than approximately 0.4 μm thick.
Claim 8
Dependent Claim
15 words
The dielectric structure of claim 2, wherein said windows have an isotropically tapered upper portion.
Claim 9
Dependent Claim
212 words
A product produced by the process of: a) depositing a first conductive layer on a semiconductor device; b) patterning said first conductive layer to form a plurality of individual conductive lines; c) forming a first dielectric layer over said conductive lines by a first film growth process; d) forming a second dielectric layer, on top of said first dielectric layer, by a second film growth process wherein said step of forming said second dielectric layer comprises reacting Si(OC 2 H 5 ) 4 and O 3 with an O 2 carrier at 60 to 100 Torr and approximately 380° C.; e) etching said second dielectric layer until a portion of said first dielectric layer is exposed; f) forming a layer of spin-on-glass over the surface of said first and second dielectric layers; g) etching said spin-on-glass layer until the surface thereof is planarized; h) forming a third dielectric layer, on top of said planarized surface utilizing said first film growth process; i) etching contact holes through said third and first dielectric layers; and j) depositing a second conductive layer on the surface comprising said third dielectric layer and said contact holes; wherein said step of depositing a first conductive layer comprises sputtering an Al-Cu alloy to a thickness of approximately 0.6 μm.
Claim 10
Dependent Claim
212 words
A product produced by the process of: a) depositing a first conductive layer on a semiconductor device; b) patterning said first conductive layer to form a plurality of individual conductive lines; c) forming a first dielectric layer over said conductive lines by a first film growth process; d) forming a second dielectric layer, on top of said first dielectric layer, by a second film growth process wherein said step of forming said second dielectric layer comprises reacting Si(OC 2 H 5 ) 4 and O 3 with an O 2 carrier at 60 to 100 Torr and approximately 380° C.; e) etching said second dielectric layer until a portion of said first dielectric layer is exposed; f) forming a layer of spin-on-glass over the surface of said first and second dielectric layers; g) etching said spin-on-glass layer until the surface thereof is planarized; h) forming a third dielectric layer, on top of said planarized surface utilizing said first film growth process; i) etching contact holes through said third and first dielectric layers; and j) depositing a second conductive layer on the surface comprising said third dielectric layer and said contact holes; wherein said step of depositing a first conductive layer comprises sputtering an Al-Cu alloy to a thickness of approximately 0.6 μm.
Claim 11
Dependent Claim
142 words
A dielectric structure for semiconductor devices having multiple conductive layers comprising: a) at least one first conductive line disposed on said semiconductor device; b) a first insulating layer formed over said at least one conductive line and said semiconductor device, such that it has a non-planar surface comprising depressed regions; c) a second insulating layer formed over said first insulating layer, such that said second insulating layer is formed as side-wall spacers at sides of said first insulating layer depressed regions, the combination of said first and second insulating layers having a non-planar surface; d) a plurality of spin-on-glass regions formed over said second insulating layer such that the combination of said spin-on-glass regions and said second insulator regions provide a substantially planar surface; and e) a third insulating layer formed over said first insulator, said second insulator and said spin-on-glass regions.
Claim 12
Dependent Claim
142 words
A dielectric structure for semiconductor devices having multiple conductive layers comprising: a) at least one first conductive line disposed on said semiconductor device; b) a first insulating layer formed over said at least one conductive line and said semiconductor device, such that it has a non-planar surface comprising depressed regions; c) a second insulating layer formed over said first insulating layer, such that said second insulating layer is formed as side-wall spacers at sides of said first insulating layer depressed regions, the combination of said first and second insulating layers having a non-planar surface; d) a plurality of spin-on-glass regions formed over said second insulating layer such that the combination of said spin-on-glass regions and said second insulator regions provide a substantially planar surface; and e) a third insulating layer formed over said first insulator, said second insulator and said spin-on-glass regions.
References Cited (Backward Citations)
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