Interlaced to non-interlaced scan converter with reduced buffer memory

Claim 1

A data converter supplied with successive scan lines of interlaced image data, pixel clock pulses and H/SYNC pulses for converting said interlaced image data in a non-interlaced format, said interlaced image data including a plurality of successive frames, each of the frames having an odd field followed by an even field, each of said scan lines including a predetermined number of pixels, said pixel clock pulses having a period corresponding to that of the pixels, each of said H/SYNC pulses announcing the beginning of the corresponding scan line of said interlaced image data, said converter comprising: a two-dimensional buffer memory capable of storing up to N of said successive scan lines of said interlaced image data for performing, per pixel clock pulse, a read and then a write operation, wherein said N represents the number of scan lines per field; a horizontal address generator for, upon receiving each of said pixel clock pulses, generating a horizontal address for the buffer memory by sequentially counting the number of pixel clock pulses received after each of said H/SYNC pulses received; an initial vertical address generator for generating, during an initial period from the receipt of the first of said H/SYNC pulses until before the receipt of the (N+1)st of said H/SYNC pulses, N vertical addresses sequentially by counting the number of H/SYNC pulses received; a subsequent vertical address generator for generating, in response to each of said H/SYNC pulses from the receipt of the (N+1)st of said H/SYNC pulses, one of a sequence of vertical addresses for outputting said interlaced image data in the non-interlaced format; and a vertical address selection means for selecting a vertical address for the buffer memory either from the initial vertical address generator during the initial period, or from the subsequent vertical address generator after the receipt of the (N+1)st of said H/SYNC pulses.