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US5372959A
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US
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Thin film transistor having a multi-layer stacked channel and its manufacturing method
Assignee: SK Hynix Inc
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Filing: 1993-06-30
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Granted: 1994-12-13
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Expires: 2013-06-30
Abstract
Abstract Disclosed is a thin film transistor used to manufacture a highly integrated SRAM or LCD and its manufacturing method, and more particularly, to a thin film transistor having a multi-layer stacked channel in order to increase the current flow during the thin film transistor's ON state by securing a enough channel width despite of the limited area. A thin film transistor on which a channel had been deposited in accordance with the present invention can be manufactured in a small area; accordingly, a highly integrated SRAM can be manufactured by decreasing the area of the unit cell of SRAM. Also, the resolution can be enhanced by decreasing the area occupied by the thin film transistor in the panel during the manufacturing process of the LCD.
Inventors
- 👤 Ha H. Chan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:00
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6757; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/6704; H10D30/6713; H10D30/6729; H10D30/673; H10D30/6733; H10D30/6734; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D30/6748; Y; Y10; Y10S; Y10S148/00; Y10S148/164
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
229 words
A method of manufacturing a thin film transistor comprising the steps of: depositing a first silicon layer on a first insulating layer; forming a second insulating layer pattern on a part of the first silicon layer; depositing a second silicon layer on the first silicon layer and the second insulating layer pattern and forming therefrom an elongated second silicon layer pattern crossing over the second insulating layer pattern; wet etching said second insulating layer pattern completely to form a tunnel between the first silicon layer and the second silicon layer; using a lithographic technique to form a first silicon layer pattern that has the same pattern as the second silicon layer pattern and to thereby form a thin film transistor gate having at two ends thereof the first silicon layer pattern connected to the second silicon layer pattern; forming a gate oxide layer on the tunnel surface of the thin film transistor gate and on top of the gate; depositing a third silicon layer on the surface of the gate oxide layer and forming a third silicon layer pattern via a lithographic technique to form a double-layered thin film transistor channel in the tunnel of the gate and on top of the gate; and forming a source and drain by implanting impurities into a part of the third silicon layer pattern that does not belong to the channel area.
Claim 2
Independent Claim
229 words
A method of manufacturing a thin film transistor comprising the steps of: depositing a first silicon layer on a first insulating layer; forming a second insulating layer pattern on a part of the first silicon layer; depositing a second silicon layer on the first silicon layer and the second insulating layer pattern and forming therefrom an elongated second silicon layer pattern crossing over the second insulating layer pattern; wet etching said second insulating layer pattern completely to form a tunnel between the first silicon layer and the second silicon layer; using a lithographic technique to form a first silicon layer pattern that has the same pattern as the second silicon layer pattern and to thereby form a thin film transistor gate having at two ends thereof the first silicon layer pattern connected to the second silicon layer pattern; forming a gate oxide layer on the tunnel surface of the thin film transistor gate and on top of the gate; depositing a third silicon layer on the surface of the gate oxide layer and forming a third silicon layer pattern via a lithographic technique to form a double-layered thin film transistor channel in the tunnel of the gate and on top of the gate; and forming a source and drain by implanting impurities into a part of the third silicon layer pattern that does not belong to the channel area.
Claim 3
Dependent Claim
28 words
The method according to claim 1, wherein said first silicon layer, second silicon layer, and third silicon layer are made of a polysilicon layer or amorphous silicon layer.
Claim 4
Dependent Claim
31 words
The method according to claim 1, wherein said source and drain are formed on the part of the third silicon layer that does not overlap with the thin film transistor gate.
Claim 5
Dependent Claim
22 words
The method according to claim 1, wherein said first and second silicon layer patterns are crossed with the third silicon layer pattern.
References Cited (Backward Citations)
US5221849A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-12 | 1998-06-13 | 1998-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-12 | 2002-06-13 | 2002-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-12 | 2006-06-13 | 2006-12-13 | $7700.00 | Window Closed / Lapsed |