Apparatus and method for testing of new operating systems through priviledged instruction trapping

Claim 1

An apparatus for debugging a new operating system within user mode of a processor having a privileged instruction execution monitor mode wherein privileged instructions are executed and a user mode wherein a privileged instruction is typically treated as a no-operation instruction, the processor comprising an instruction execution unit which executes an instruction parcel having an opcode, the processor further comprising a current instruction parcel register, connected to the instruction execution unit, which receives the instruction parcel before passing the instruction parcel to the instruction execution unit, the apparatus comprising: processor interrupt means, connected to the current instruction parcel register and the instruction execution unit, for generating a hardware interrupt to said instruction execution unit on encountering a privileged instruction during user mode, wherein the processor interrupt means comprise an interrupt generator which generates the hardware interrupt when the instruction parcel opcode received by the current instruction parcel register is associated with a privileged instruction; and interrupt enable means connected to said processor interrupt means for disabling said hardware interrupt, wherein the interrupt enable means comprise a mode select register connected to the interrupt generator, wherein the mode select register comprises a mode select bit which operates to prevent issuance of the hardware interrupt by the interrupt generator.

Claim 2

An apparatus for debugging a new operating system within user mode of a processor having a privileged instruction execution monitor mode wherein privileged instructions are executed and a user mode wherein a privileged instruction is typically treated as a no-operation instruction, the processor comprising an instruction execution unit which executes an instruction parcel having an opcode, the processor further comprising a current instruction parcel register, connected to the instruction execution unit, which receives the instruction parcel before passing the instruction parcel to the instruction execution unit, the apparatus comprising: processor interrupt means, connected to the current instruction parcel register and the instruction execution unit, for generating a hardware interrupt to said instruction execution unit on encountering a privileged instruction during user mode, wherein the processor interrupt means comprise an interrupt generator which generates the hardware interrupt when the instruction parcel opcode received by the current instruction parcel register is associated with a privileged instruction; and interrupt enable means connected to said processor interrupt means for disabling said hardware interrupt, wherein the interrupt enable means comprise a mode select register connected to the interrupt generator, wherein the mode select register comprises a mode select bit which operates to prevent issuance of the hardware interrupt by the interrupt generator.

Claim 4

A method of emulating an operating system having a privileged instruction within user mode of a vector processing computer having both a user mode and a privileged instruction executing monitor mode, comprising the steps of: providing a processing unit comprising an instruction execution unit, a current instruction register, an interrupt generator and a mode select register comprising a mode select bit having a first and a second logic state; providing a sequence of instructions, wherein the sequence of instructions includes a first instruction followed by a second instruction and wherein the first instruction is a privileged instruction; storing the first instruction in the current instruction register; if the mode select bit is in the first logic state: generating, from the interrupt generator to the instruction execution unit, a hardware interrupt associated with the privileged instruction; performing a packet exchange sequence to enter privileged instruction executing mode; executing, in privileged instruction mode, a series of instructions which emulate execution of the privileged instruction; and returning to user mode to fetch the second instruction; and otherwise, treating the first instruction as a NO-OP instruction and fetching the second instruction.

Claim 5

A method of emulating an operating system having a privileged instruction within user mode of a vector processing computer having both a user mode and a privileged instruction executing monitor mode, comprising the steps of: providing a processing unit comprising an instruction execution unit, a current instruction register, an interrupt generator and a mode select register comprising a mode select bit having a first and a second logic state; providing a sequence of instructions, wherein the sequence of instructions includes a first instruction followed by a second instruction and wherein the first instruction is a privileged instruction; storing the first instruction in the current instruction register; if the mode select bit is in the first logic state: generating, from the interrupt generator to the instruction execution unit, a hardware interrupt associated with the privileged instruction; performing a packet exchange sequence to enter privileged instruction executing mode; executing, in privileged instruction mode, a series of instructions which emulate execution of the privileged instruction; and returning to user mode to fetch the second instruction; and otherwise, treating the first instruction as a NO-OP instruction and fetching the second instruction.

Claim 6

A method of testing program code for a new operating system in a computer having both a user mode and a privileged instruction executing monitor mode, wherein the program code includes a privileged instruction, the method comprising the steps of: providing a hardware interrupt circuit for generating a hardware interrupt when the privileged instruction is detected while the computer is in said user mode; enabling the hardware interrupt circuit; placing the computer in user mode; loading the new operating system and executing the new operating system program code within the user mode; trapping the privileged instruction, wherein the step of trapping the privileged instruction comprises: detecting the privileged instruction; and generating the hardware interrupt when the privileged instruction is detected; switching to the monitor mode; and emulating the privileged instruction.

Claim 7

A method of testing program code for a new operating system in a computer having both a user mode and a privileged instruction executing monitor mode, wherein the program code includes a privileged instruction, the method comprising the steps of: providing a hardware interrupt circuit for generating a hardware interrupt when the privileged instruction is detected while the computer is in said user mode; enabling the hardware interrupt circuit; placing the computer in user mode; loading the new operating system and executing the new operating system program code within the user mode; trapping the privileged instruction, wherein the step of trapping the privileged instruction comprises: detecting the privileged instruction; and generating the hardware interrupt when the privileged instruction is detected; switching to the monitor mode; and emulating the privileged instruction.