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US5371701A
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Stacked delta cell capacitor
Assignee: Micron Technology Inc
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Filing: 1994-04-05
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Granted: 1994-12-06
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Expires: 2014-04-05
Abstract
Abstract A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.
Inventors
- 👤 Ruojia Lee
- 👤 Charles H. Dennison
- 👤 Yauh-Ching Liu
- 👤 Pierre Fazan
- 👤 Steven D. Cummings
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 15:04
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
165 words
A stacked capacitor fabricated in a semiconductor device, said stacked capacitor comprising: a first conductive layer, said first conductive layer forming first and second inverted deltoid components, each of which having a downward apex and upward peaks, said first conductive layer making contact to a diffusion junction at said first inverted deltoid apex, said second inverted deltoid apex being isolated from an adjacent diffusion junction by an isolating layer; a second conductive layer having top and bottom surfaces planarly spanning said first conductive layer, said bottom surface of said second conductive layer making contact to said peaks of said first conductive layer forming a hollowness therein, said second conductive layer combining with said first conductive layer thereby forming a first capacitor electrode: a capacitor dielectric layer being adjacent said first capacitor electrode and coextensive therewith; and a third conductive layer forming a second capacitor electrode, said second capacitor electrode having upper and lower surfaces and being adjacent to said capacitor dielectric layer and coextensive therewith.
Claim 2
Dependent Claim
165 words
A stacked capacitor fabricated in a semiconductor device, said stacked capacitor comprising: a first conductive layer, said first conductive layer forming first and second inverted deltoid components, each of which having a downward apex and upward peaks, said first conductive layer making contact to a diffusion junction at said first inverted deltoid apex, said second inverted deltoid apex being isolated from an adjacent diffusion junction by an isolating layer; a second conductive layer having top and bottom surfaces planarly spanning said first conductive layer, said bottom surface of said second conductive layer making contact to said peaks of said first conductive layer forming a hollowness therein, said second conductive layer combining with said first conductive layer thereby forming a first capacitor electrode: a capacitor dielectric layer being adjacent said first capacitor electrode and coextensive therewith; and a third conductive layer forming a second capacitor electrode, said second capacitor electrode having upper and lower surfaces and being adjacent to said capacitor dielectric layer and coextensive therewith.
Claim 3
Dependent Claim
14 words
The stacked capacitor as recited in claim 1, wherein said isolating layer is oxide.
Claim 4
Dependent Claim
20 words
The stacked capacitor as recited in claim 1, wherein said first, second and third conductive layers are conductively doped polysilicon.
Claim 5
Dependent Claim
15 words
The stacked capacitor as recited in claim 1, wherein said conductively doped polysilicon is p-type.
Claim 6
Dependent Claim
20 words
The stacked capacitor as recited in claim 1, wherein said first and said second polysilicon has a rugged, textured surface.
Claim 7
Dependent Claim
172 words
A dynamic random access memory (DRAM) having a stacked capacitor fabricated therein, said stacked capacitor comprising: a conductively-doped first polysilicon layer, said first polysilicon layer forming first and second inverted deltoid components, each of which having a downward apex and upward peaks, said first polysilicon layer making contact to a diffusion junction at said first inverted deltoid apex, said second inverted deltoid apex being isolated from an adjacent diffusion junction by an isolating layer; a conductively-doped second polysilicon layer having top and bottom surfaces planarly spanning said first polysilicon layer, said bottom surface of said second polysilicon layer making contact to said peaks of said first polysilicon layer forming a hollowness therein, said second polysilicon layer combining with said first polysilicon layer thereby forming a first capacitor electrode; a capacitor dielectric layer being adjacent said first capacitor electrode and coextensive therewith; and a conductively-doped third polysilicon layer forming a second capacitor electrode, said second capacitor electrode having upper and lower surfaces and being adjacent to said capacitor dielectric layer and coextensive therewith.
Claim 8
Dependent Claim
172 words
A dynamic random access memory (DRAM) having a stacked capacitor fabricated therein, said stacked capacitor comprising: a conductively-doped first polysilicon layer, said first polysilicon layer forming first and second inverted deltoid components, each of which having a downward apex and upward peaks, said first polysilicon layer making contact to a diffusion junction at said first inverted deltoid apex, said second inverted deltoid apex being isolated from an adjacent diffusion junction by an isolating layer; a conductively-doped second polysilicon layer having top and bottom surfaces planarly spanning said first polysilicon layer, said bottom surface of said second polysilicon layer making contact to said peaks of said first polysilicon layer forming a hollowness therein, said second polysilicon layer combining with said first polysilicon layer thereby forming a first capacitor electrode; a capacitor dielectric layer being adjacent said first capacitor electrode and coextensive therewith; and a conductively-doped third polysilicon layer forming a second capacitor electrode, said second capacitor electrode having upper and lower surfaces and being adjacent to said capacitor dielectric layer and coextensive therewith.
Claim 9
Dependent Claim
14 words
The DRAM capacitor as recited in claim 6, wherein said isolating layer is oxide.
Claim 10
Dependent Claim
12 words
The DRAM as recited in claim 6, wherein said conductive-doping is p-type.
Claim 11
Dependent Claim
20 words
The DRAM capacitor as recited in claim 6, wherein said first and said second polysilicon has a rugged, textured surface.
References Cited (Backward Citations)
US5285092A
Cited
US5130885A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-05 | 1998-06-06 | 1998-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-05 | 2002-06-06 | 2002-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-05 | 2006-06-06 | 2006-12-06 | $7700.00 | Window Closed / Lapsed |