Patent US5371479A successfully refreshed from Google Patents.
US5371479A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pre-amplifier with multi-stage feedback
Assignee: United States Department of the Navy
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Filing: 1994-03-22
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Granted: 1994-12-06
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Expires: 2014-03-22
Abstract
Abstract A circuit for amplifying an input signal comprises an operational amplifi a dual operational amplifier, and a buffering operational amplifier all cascaded in the aforementioned order. The first operational amplifier amplifies the input signal with minimum noise degradation, is set up as a non-inverting amplifier stage, and has a local negative feedback loop comprising a resistor and capacitor in parallel. The dual operational amplifier has two amplifying devices. One device forms a second amplifying stage which increases the gain of the pre-amplified input signal and has a local negative feedback loop comprising a resistor. The other device is a third operational amplifier which combines with the buffering operational amplifier to form an amplifying and buffering stage. The third operational amplifier connects in series to the output of the second amplifying stage. The buffering operational amplifier connects in series to the output of the third operational amplifier and buffers the amplified signal at this output. The amplifying and buffering stage has a two-stage feedback loop comprising a resistor connected between the output of the buffering operational amplifier and the inverting input of the third operational amplifier. A four-stage feedback loop includes a resistor and capacitor in parallel and connects between the output of the buffering operational amplifier and the inverting input of the first operational amplifier.
Inventors
- 👤 James D. Hagerty
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:58
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/34; H03F3/343; H03F3/347; H03F1/00; H03F1/34
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
286 words
A circuit for amplifying an input signal, comprising: first means for amplifying the input signal, said means for amplifying having an inverting input, a noninverting input and an output, the noninverting input being connected to the input signal, said first means for amplifying having a first local feedback loop connected between the output and the inverting input of said first means for amplifying; second means, connected to the output of said first means for amplifying, for amplifying the amplified input signal, said second means for amplifying having an inverting input, a noninverting input and an output, the inverting input being connected to the output of said first means for amplifying, said second means for amplifying having a second local feedback loop connected between the output and the inverting input of said second means for amplifying; means, connected to the output of said second means for amplifying, for amplifying and buffering the amplified input signal, said means for amplifying and buffering comprising a third means for amplifying having an inverting input, a noninverting input, and an output, the inverting input connected to the output of said second means for amplifying, said means for amplifying and buffering further comprising means for buffering the amplified signal, the means for buffering having an input and an output, the input of the means for buffering being connected to the output of the third means for amplifying, said means for amplifying and buffering further comprising a two-stage feedback loop connected between the output of the means for buffering and the inverting input of the third means for amplifying; and an interstage feedback loop connected between the output of the means for buffering and the inverting input of said first means for amplifying.
Claim 2
Dependent Claim
286 words
A circuit for amplifying an input signal, comprising: first means for amplifying the input signal, said means for amplifying having an inverting input, a noninverting input and an output, the noninverting input being connected to the input signal, said first means for amplifying having a first local feedback loop connected between the output and the inverting input of said first means for amplifying; second means, connected to the output of said first means for amplifying, for amplifying the amplified input signal, said second means for amplifying having an inverting input, a noninverting input and an output, the inverting input being connected to the output of said first means for amplifying, said second means for amplifying having a second local feedback loop connected between the output and the inverting input of said second means for amplifying; means, connected to the output of said second means for amplifying, for amplifying and buffering the amplified input signal, said means for amplifying and buffering comprising a third means for amplifying having an inverting input, a noninverting input, and an output, the inverting input connected to the output of said second means for amplifying, said means for amplifying and buffering further comprising means for buffering the amplified signal, the means for buffering having an input and an output, the input of the means for buffering being connected to the output of the third means for amplifying, said means for amplifying and buffering further comprising a two-stage feedback loop connected between the output of the means for buffering and the inverting input of the third means for amplifying; and an interstage feedback loop connected between the output of the means for buffering and the inverting input of said first means for amplifying.
Claim 3
Dependent Claim
23 words
A circuit for amplifying an input signal as recited in claim 1 wherein said first means for amplifying includes a low-noise operational amplifier.
Claim 4
Dependent Claim
43 words
A circuit for amplifying an input signal as recited in claim 1 wherein the first local feedback loop includes a resistor and a capacitor connected in parallel and a resistor connected between the inverting input of said first means for amplifying and ground.
Claim 5
Dependent Claim
53 words
A circuit for amplifying an input signal as recited in claim 1 wherein said first means for amplifying further comprises a low-noise diode connected between a positive voltage supply line and the noninverting input of said first means for amplifying, the low-noise diode having a cathode connected to the positive voltage supply line.
Claim 6
Dependent Claim
53 words
A circuit for amplifying an input signal as recited in claim 1 wherein said first means for amplifying further comprises a low-noise diode connected between a negative voltage supply line and the noninverting input of said first means for amplifying, the low-noise diode having an anode connected to the negative voltage supply line.
Claim 7
Dependent Claim
35 words
A circuit for amplifying an input signal as recited in claim 1 wherein said first means for amplifying further comprises a resistor connected between the noninverting input of said first means for amplifying and ground.
Claim 8
Dependent Claim
22 words
A circuit for amplifying an input signal as recited in claim 1 wherein said second means for amplifying includes an operational amplifier.
Claim 9
Dependent Claim
50 words
A circuit for amplifying an input signal as recited in claim 1 wherein the second local feedback loop includes a resistor connected between the inverting input and the output of said second means for amplifying and wherein the noninverting input of said second means for amplifying is connected to ground.
Claim 10
Dependent Claim
44 words
A circuit for amplifying an input signal as recited in claim 1 wherein said second means for amplifying further comprises a resistor connected in series from the output of said first means for amplifying to the inverting input of said second means for amplifying.
Claim 11
Dependent Claim
36 words
A circuit for amplifying an input signal as recited in claim 1 wherein said second means for amplifying and the third means for amplifying of said means for amplifying and buffering comprise a dual operational amplifier.
Claim 12
Dependent Claim
29 words
A circuit for amplifying an input signal as recited in claim 1 wherein the third means for amplifying of said means for amplifying and buffering is an operational amplifier.
Claim 13
Dependent Claim
23 words
A circuit for amplifying an input signal as recited in claim 1 wherein said means for amplifying and buffering includes a buffer amplifier.
Claim 14
Dependent Claim
39 words
A circuit for amplifying an input signal as recited in claim 1 wherein the two-stage feedback loop includes a resistor connected between the output of the means for buffering and the inverting input of the third means for amplifying.
Claim 15
Dependent Claim
26 words
A circuit for amplifying an input signal as recited in claim 1 wherein the noninverting input of the third means for amplifying is connected to ground.
Claim 16
Dependent Claim
43 words
A circuit for amplifying an input signal as recited in claim 1 wherein said means for amplifying and buffering further comprises a resistor connected between the output of said second means for amplifying and the inverting input of the third means for amplifying.
Claim 17
Dependent Claim
37 words
A circuit for amplifying an input signal as recited in claim 1 wherein said means for amplifying and buffering further comprises a capacitor connected between the output and the inverting input of the third means for amplifying.
Claim 18
Dependent Claim
41 words
A circuit for amplifying an input signal as recited in claim 1 wherein said means for amplifying and buffering further comprises a capacitor connected between a positive voltage supply line and a negative voltage supply line of the means for buffering.
Claim 19
Dependent Claim
26 words
A circuit for amplifying an input signal as recited in claim 1 wherein said interstage feedback loop includes a resistor and a capacitor connected in parallel.
Claim 20
Dependent Claim
26 words
A circuit for amplifying an input signal as recited in claim 1 further comprising an output terminal connected to the output of the means for buffering.
Claim 21
Dependent Claim
33 words
A circuit for amplifying an input signal as recited in claim 19 further comprising a capacitor connected between the output of the means for buffering and said output terminal for alternating current coupling.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-05 | 1998-06-06 | 1998-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-05 | 2002-06-06 | 2002-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-05 | 2006-06-06 | 2006-12-06 | $7700.00 | Window Closed / Lapsed |