Locos technology with narrow silicon trench

Claim 1

A method of forming a device isolation region of an integrated circuit by means of stress-releasing narrow silicon trenches comprising: providing an insulating layer over the surface of a silicon substrate; depositing a silicon nitride layer overlying said insulating layer; depositing a silicon dioxide layer overlying said silicon nitride layer; etching away portions of said silicon dioxide, said silicon nitride, and said insulating layers not covered by a mask to provide an opening to said silicon substrate where said device isolation region is to be formed; etching into said silicon substrate through the opening to form a shallow trench within said opening where said device isolation region is to be formed wherein said shallow trench will provide space for said silicon substrate to expand during subsequent oxidation to provide a fully-recessed surface of said device isolation region; forming silicon dioxide spacers on the sidewalls of said opening and on the trench sidewalls; forming silicon nitride spacers on the sidewalls of said silicon dioxide spacers and over the trench sidewalls; coating said silicon substrate with a spin-on-glass layer and curing said spin-on-glass layer; etching back said spin-on-glass layer wherein said spin-on-glass layer remains only within said shallow trench not covered by said silicon dioxide and said silicon nitride spacers; stripping said silicon nitride spacers wherein said silicon substrate within said shallow trench is exposed under said silicon nitride spacers; etching narrow trenches into said silicon substrate where said silicon substrate is exposed under said stripped silicon nitride spacers and wherein said narrow trenches will act to relieve stress during subsequent oxidation; removing said silicon dioxide spacers and said spin-on-glass layer wherein said opening where said device isolation region is to be formed is entirely exposed; selectively ion implanting channel-stops through said opening into said substrate underneath said shallow trench and underneath said narrow trenches; oxidizing said silicon substrate within said opening wherein said silicon substrate is transformed to silicon dioxide and wherein said silicon dioxide expands to fill said narrow trenches and wherein said narrow trenches act to relieve stress within said silicon substrate; and removing said silicon nitride layer and said first insulating layer completing said fully-recessed device isolation of said integrated circuit.

Claim 2

A method of forming a device isolation region of an integrated circuit by means of stress-releasing narrow silicon trenches comprising: providing an insulating layer over the surface of a silicon substrate; depositing a silicon nitride layer overlying said insulating layer; depositing a silicon dioxide layer overlying said silicon nitride layer; etching away portions of said silicon dioxide, said silicon nitride, and said insulating layers not covered by a mask to provide an opening to said silicon substrate where said device isolation region is to be formed; etching into said silicon substrate through the opening to form a shallow trench within said opening where said device isolation region is to be formed wherein said shallow trench will provide space for said silicon substrate to expand during subsequent oxidation to provide a fully-recessed surface of said device isolation region; forming silicon dioxide spacers on the sidewalls of said opening and on the trench sidewalls; forming silicon nitride spacers on the sidewalls of said silicon dioxide spacers and over the trench sidewalls; coating said silicon substrate with a spin-on-glass layer and curing said spin-on-glass layer; etching back said spin-on-glass layer wherein said spin-on-glass layer remains only within said shallow trench not covered by said silicon dioxide and said silicon nitride spacers; stripping said silicon nitride spacers wherein said silicon substrate within said shallow trench is exposed under said silicon nitride spacers; etching narrow trenches into said silicon substrate where said silicon substrate is exposed under said stripped silicon nitride spacers and wherein said narrow trenches will act to relieve stress during subsequent oxidation; removing said silicon dioxide spacers and said spin-on-glass layer wherein said opening where said device isolation region is to be formed is entirely exposed; selectively ion implanting channel-stops through said opening into said substrate underneath said shallow trench and underneath said narrow trenches; oxidizing said silicon substrate within said opening wherein said silicon substrate is transformed to silicon dioxide and wherein said silicon dioxide expands to fill said narrow trenches and wherein said narrow trenches act to relieve stress within said silicon substrate; and removing said silicon nitride layer and said first insulating layer completing said fully-recessed device isolation of said integrated circuit.

Claim 13

The method of field oxidation of an integrated circuit wherein said field oxidation has a fully recessed surface and wherein said field oxidation has a small bird's beak comprising: providing a pad silicon oxide layer over the surface of a silicon substrate; depositing a silicon nitride layer overlying said pad silicon oxide layer; depositing a silicon dioxide layer overlying said silicon nitride layer; etching away portions of said silicon dioxide, said silicon nitride, and said pad silicon oxide layers not covered by a mask to provide an opening to said silicon substrate where said field oxidation region is to be formed; etching into said silicon substrate through the opening to form a shallow trench within said opening where said field oxidation region is to be formed wherein said shallow trench will provide space for said silicon substrate to expand during subsequent oxidation to provide a fully-recessed surface of said field oxidation region; forming silicon dioxide spacers on the sidewalls of said opening and on the trench sidewalls; forming silicon nitride spacers on the sidewalls of said silicon dioxide spacers and over the trench sidewalls; coating said silicon substrate with a spin-on-glass layer and curing said spin-on-glass layer; etching back said spin-on-glass layer wherein said spin-on-glass layer remains only within said shallow trench not covered by said silicon dioxide and said silicon nitride spacers; stripping away said silicon nitride spacers wherein said silicon substrate within said shallow trench is exposed under said silicon nitride spacers; etching narrow trenches into said silicon substrate where said silicon substrate is exposed under said stripped silicon nitride spacers and wherein said narrow trenches will act to relieve stress during subsequent oxidation; removing said silicon dioxide spacers and said spin-on-glass layer wherein said opening where said field oxidation region is to be formed is entirely exposed; selectively ion implanting channel-stops through said opening and on the trench sidewalls into said substrate underneath said shallow trench and underneath said narrow trenches; oxidizing said silicon substrate within said opening wherein said silicon substrate is transformed to silicon dioxide and wherein said silicon dioxide expands to fill said narrow trenches and wherein said narrow trenches act to relieve stress within said silicon substrate and wherein said silicon dioxide expands vertically to provide a fully recessed surface of said field oxidation region; and removing said silicon nitride layer and said pad silicon oxide layer completing said fully-recessed field oxidation of said integrated circuit.

Claim 14

The method of field oxidation of an integrated circuit wherein said field oxidation has a fully recessed surface and wherein said field oxidation has a small bird's beak comprising: providing a pad silicon oxide layer over the surface of a silicon substrate; depositing a silicon nitride layer overlying said pad silicon oxide layer; depositing a silicon dioxide layer overlying said silicon nitride layer; etching away portions of said silicon dioxide, said silicon nitride, and said pad silicon oxide layers not covered by a mask to provide an opening to said silicon substrate where said field oxidation region is to be formed; etching into said silicon substrate through the opening to form a shallow trench within said opening where said field oxidation region is to be formed wherein said shallow trench will provide space for said silicon substrate to expand during subsequent oxidation to provide a fully-recessed surface of said field oxidation region; forming silicon dioxide spacers on the sidewalls of said opening and on the trench sidewalls; forming silicon nitride spacers on the sidewalls of said silicon dioxide spacers and over the trench sidewalls; coating said silicon substrate with a spin-on-glass layer and curing said spin-on-glass layer; etching back said spin-on-glass layer wherein said spin-on-glass layer remains only within said shallow trench not covered by said silicon dioxide and said silicon nitride spacers; stripping away said silicon nitride spacers wherein said silicon substrate within said shallow trench is exposed under said silicon nitride spacers; etching narrow trenches into said silicon substrate where said silicon substrate is exposed under said stripped silicon nitride spacers and wherein said narrow trenches will act to relieve stress during subsequent oxidation; removing said silicon dioxide spacers and said spin-on-glass layer wherein said opening where said field oxidation region is to be formed is entirely exposed; selectively ion implanting channel-stops through said opening and on the trench sidewalls into said substrate underneath said shallow trench and underneath said narrow trenches; oxidizing said silicon substrate within said opening wherein said silicon substrate is transformed to silicon dioxide and wherein said silicon dioxide expands to fill said narrow trenches and wherein said narrow trenches act to relieve stress within said silicon substrate and wherein said silicon dioxide expands vertically to provide a fully recessed surface of said field oxidation region; and removing said silicon nitride layer and said pad silicon oxide layer completing said fully-recessed field oxidation of said integrated circuit.