US5371035A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming electrical isolation in an integrated circuit device
Assignee: Motorola Solutions Inc
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Filing: 1993-02-01
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Granted: 1994-12-06
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Expires: 2013-02-01
Abstract
Abstract A layer of silicon-germanium (57) allows electrical isolation structures, having reduced field oxide encroachment, to be formed without adversely effecting the adjacent active regions (64). A high etch selectivity between silicon-germanium and the silicon substrate (52) allows the silicon-germanium layer (57) to be removed, after field oxidation, without damaging the underlying active regions (64).
Inventors
- 👤 James R. Pfiester
- 👤 Philip J. Tobin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:03
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/61; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
105 words
A method for forming electrical isolation in an integrated circuit device comprising the steps of: providing a semiconductor substrate; forming a buffer layer overlying the substrate; forming a silicon-germanium layer overlying the buffer layer; forming an oxidation resistant layer overlying the silicon-germanium layer; patterning the oxidation resistant layer to define an isolation region of the substrate, and to leave a remaining portion of the oxidation resistant layer overlying the substrate; oxidizing the isolation region of the substrate to form electrical isolation in the isolation region of the substrate; removing the remaining portion of the oxidation resistant layer; and applying a silicon-germanium etchant to the substrate.
Claim 2
Independent Claim
105 words
A method for forming electrical isolation in an integrated circuit device comprising the steps of: providing a semiconductor substrate; forming a buffer layer overlying the substrate; forming a silicon-germanium layer overlying the buffer layer; forming an oxidation resistant layer overlying the silicon-germanium layer; patterning the oxidation resistant layer to define an isolation region of the substrate, and to leave a remaining portion of the oxidation resistant layer overlying the substrate; oxidizing the isolation region of the substrate to form electrical isolation in the isolation region of the substrate; removing the remaining portion of the oxidation resistant layer; and applying a silicon-germanium etchant to the substrate.
Claim 3
Dependent Claim
27 words
The method of claim 1 wherein the step of applying the silicon-germanium etchant is further characterized as applying a wet etchant comprising hydrofluoric acid and hydrogen peroxide.
Claim 4
Dependent Claim
27 words
The method of claim 1 wherein the step of applying the silicon-germanium etchant is further characterized as applying a wet etchant comprising hydrofluoric acid and nitric acid.
Claim 5
Dependent Claim
27 words
The method of claim 1 wherein the step of applying the silicon-germanium etchant is further characterized as applying a wet etchant comprising ammonium hydroxide and hydrogen peroxide.
Claim 6
Independent Claim
195 words
A method for forming electrical isolation in an integrated circuit device comprising the steps of: providing a substrate; forming a first buffer layer overlying the substrate; forming an oxidation resistant layer overlying the first buffer layer; patterning the oxidation resistant layer to form an exposed portion of the first buffer layer, and to leave a remaining portion of the oxidation resistant layer overlying the substrate, and to define an isolation region of the substrate; etching the exposed portion of the first buffer layer to form a recess under an edge portion of the remaining portion of the oxidation resistant layer, and to form an exposed portion of the substrate, and to leave a remaining portion of the buffer layer overlying the substrate; forming a second buffer layer overlying the exposed portion of the substrate; forming a silicon-germanium layer overlying the remaining portion of the oxidation resistant layer and the second buffer layer wherein the silicon-germanium layer substantially fills the recess; oxidizing the isolation region of the substrate to form electrical isolation in the isolation region of the substrate; removing the remaining portion of the oxidation resistant layer; and applying a silicon-germanium etchant to the substrate.
Claim 7
Independent Claim
195 words
A method for forming electrical isolation in an integrated circuit device comprising the steps of: providing a substrate; forming a first buffer layer overlying the substrate; forming an oxidation resistant layer overlying the first buffer layer; patterning the oxidation resistant layer to form an exposed portion of the first buffer layer, and to leave a remaining portion of the oxidation resistant layer overlying the substrate, and to define an isolation region of the substrate; etching the exposed portion of the first buffer layer to form a recess under an edge portion of the remaining portion of the oxidation resistant layer, and to form an exposed portion of the substrate, and to leave a remaining portion of the buffer layer overlying the substrate; forming a second buffer layer overlying the exposed portion of the substrate; forming a silicon-germanium layer overlying the remaining portion of the oxidation resistant layer and the second buffer layer wherein the silicon-germanium layer substantially fills the recess; oxidizing the isolation region of the substrate to form electrical isolation in the isolation region of the substrate; removing the remaining portion of the oxidation resistant layer; and applying a silicon-germanium etchant to the substrate.
Claim 8
Dependent Claim
27 words
The method of claim 5 wherein the step of applying the silicon-germanium etchant is further characterized as applying a wet etchant comprising hydrofluoric acid and hydrogen peroxide.
Claim 9
Dependent Claim
27 words
The method of claim 5 wherein the step of applying the silicon-germanium etchant is further characterized as applying a wet etchant comprising hydrofluoric acid and nitric acid.
Claim 10
Dependent Claim
27 words
The method of claim 5 wherein the step of applying the silicon-germanium etchant is further characterized as applying a wet etchant comprising ammonium hydroxide and hydrogen peroxide.
References Cited (Backward Citations)
JPS5976472A
Cited
US4561172A
Cited
JPH02132830A
Cited
US5093277A
Cited
JPH02268434A
Cited
US4927780A
Cited
US5196437A
Cited
US5215935A
Cited
JPH0574764A
Cited
US5175123A
Cited
US5192707A
Cited
US5260229A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-12-05 | 1998-06-06 | 1998-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-12-05 | 2002-06-06 | 2002-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-12-05 | 2006-06-06 | 2006-12-06 | $7700.00 | Window Closed / Lapsed |