Interface circuit capable of performing exact data transfer

Claim 1

An interface circuit for performing a data transfer between a first device operated responsive to a first clock signal and a second device operated responsive to an asynchronous second clock signal having the same frequency as the first clock signal, said interface circuit comprising: control circuit means for generating a one-shot pulse within a period of a second clock signal whenever both one first clock signal and one second clock signal are input; first latch means for latching data inputted to the interface circuit in response to the first clock signal, second latch means for latching the data outputted from the first latch means in response to the one-shot pulse generated by the control circuit means; and third latch means for latching the data outputted from the second latch means in response to the second clock signal, the inputs and outputs of the first, second and third latch means being connected in cascade; the first clock signal being one of either the external clock signal or the internal clock signal; the second clock signal being the other of the external clock signal and the internal clock signal; and the interface circuit outputting the output signal of the third latch means synchronously with the second clock signal, and outputting data responsive to the input data even when jitter occurs in the first and second clock signals.