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US5369291A Expired / Lapsed US ⏱️ 0.0 years remaining

Voltage controlled thyristor

Assignee: SunPower Corp
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Filing: 1993-05-28
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Granted: 1994-11-29
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Expires: 2013-05-28
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Abstract

Abstract A voltage controlled thyristor includes an intrinsic layer of material between an anode and a cathode and a gate region between the intrinsic layer and the cathode comprising a lightly doped P type layer with more heavily doped P type regions extending through the lightly doped layer into the intrinsic layer. The more heavily doped P type regions are interspersed among shallower N doped regions of the cathode. In a preferred embodiment, interdigitated ohmic contacts are formed on one surface to the N doped cathode regions and the P doped regions of the control gate. In a preferred embodiment, the anode and cathode emitters have a porous construction in which a lightly doped layer or region has a more heavily doped region or regions therein.

Inventors

  • 👤 Richard M. Swanson

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 01:58
CPC Classifications
H; H10; H10D; H10D18/00; H10D8/00; H10D8/60

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 330 words
A voltage controlled thyristor comprising a semiconductor body having first and second major opposing surfaces and an intrinsic body region therebetween, a first layer of semiconductor material abutting said first surface, said first layer including P type dopants of a first concentration, a first plurality of P type doped regions in said first layer having dopant of a second concentration greater than said first concentration, said second concentration being on the order of 3×10 17 dopant atoms per cm 3 ; a second layer of semiconductor material between said intrinsic body region and said first layer of semiconductor material, said second layer including N type dopant of a third concentration, said third concentration being on the order of 1×10 18 dopant atoms per cm 3 ; a third layer of semiconductor material abutting said second surface and said intrinsic body region, said third layer including P type dopants of a fourth concentration, said fourth concentration being on the order of 1×10 17 dopant atoms per cm 3 ; a first plurality of N type doped regions in said third layer having dopant of a fifth concentration, a second plurality of N type doped regions in said first plurality of N type doped regions having dopant of a sixth concentration greater than said fifth concentration, said sixth concentration being on the order of 1×10 18 dopant atoms per cm 3 a second plurality of P type doped regions extending from said second surface through said third layer into said intrinsic body region, said second plurality of P type doped regions being interspersed among said first plurality of N type doped regions and having a dopant concentration greater than said fourth concentration, said first layer and said first plurality of P type doped regions comprising an anode, said first plurality of N doped regions and said second plurality of N doped regions comprising a cathode, and said third layer and said second plurality of P type doped regions comprising a control gate.
Claim 2
Dependent Claim 330 words
A voltage controlled thyristor comprising a semiconductor body having first and second major opposing surfaces and an intrinsic body region therebetween, a first layer of semiconductor material abutting said first surface, said first layer including P type dopants of a first concentration, a first plurality of P type doped regions in said first layer having dopant of a second concentration greater than said first concentration, said second concentration being on the order of 3×10 17 dopant atoms per cm 3 ; a second layer of semiconductor material between said intrinsic body region and said first layer of semiconductor material, said second layer including N type dopant of a third concentration, said third concentration being on the order of 1×10 18 dopant atoms per cm 3 ; a third layer of semiconductor material abutting said second surface and said intrinsic body region, said third layer including P type dopants of a fourth concentration, said fourth concentration being on the order of 1×10 17 dopant atoms per cm 3 ; a first plurality of N type doped regions in said third layer having dopant of a fifth concentration, a second plurality of N type doped regions in said first plurality of N type doped regions having dopant of a sixth concentration greater than said fifth concentration, said sixth concentration being on the order of 1×10 18 dopant atoms per cm 3 a second plurality of P type doped regions extending from said second surface through said third layer into said intrinsic body region, said second plurality of P type doped regions being interspersed among said first plurality of N type doped regions and having a dopant concentration greater than said fourth concentration, said first layer and said first plurality of P type doped regions comprising an anode, said first plurality of N doped regions and said second plurality of N doped regions comprising a cathode, and said third layer and said second plurality of P type doped regions comprising a control gate.
Claim 3
Dependent Claim 16 words
The voltage controlled thyristor as defined by claim 1 wherein said semiconductor body comprises monocrystalline silicon.
Claim 4
Dependent Claim 44 words
The voltage controlled thyristor as defined by claim 1 and further including an ohmic contact on said first surface to said anode, an ohmic contact on said second surface to said cathode, and an ohmic contact on said second surface to said control gate.
Claim 5
Dependent Claim 26 words
The voltage controlled thyristor as defined by claim 3 wherein said ohmic contact to said cathode and said ohmic contact to said control gate are interdigitated.
Claim 6
Dependent Claim 16 words
The voltage controlled thyristor as defined by claim 4 wherein said semiconductor body comprises monocrystalline silicon.

References Cited (Backward Citations)

US4935798A Cited
US4587547A Cited
JPH025569A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-11-28 1998-05-30 1998-11-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-11-28 2002-05-30 2002-11-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-11-28 2006-05-30 2006-11-29 $7700.00 Window Closed / Lapsed

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