Bus-to-bus interface for preventing data incoherence in a multiple processor computer system

Claim 2

In a multiple processor computer system having a first bus means and a second bus means, a bus-to-bus interface for coupling said first bus means to said second bus means such that data coherence is preserved, wherein said first bus means is coupled to at least one first bus master and operates according to a first protocol where each first bus master is self-identifying, and wherein said second bus means is coupled to at least one second bus master and a plurality of slaves and operates according to a second protocol where devices coupled to said second bus means are not self-identifying, said bus-to-bus interface comprising: protocol means including protocol conversion means coupled to said first arid second bus means for permitting transfer of data between said first and second bus masters and said slaves; directory means, coupled to said protocol means, for maintaining a status for each of said plurality of slaves, for determining that a first slave is performing a task for a disconnected master, said disconnected master being a bus master that is coupled to a one of said first bus means and said second bus means, said disconnected master having commanded the first slave to perform said task and subsequently relinquished said second bus means, the directory means for establishing an identity for said disconnected master and for associating the identity of the disconnected master with the first slave such that only said disconnected master is permitted to access the first slave; and rerun means, coupled to said first and second bus means and to said protocol means, for issuing a rerun command when a one of said at least one first bus master and said at least one second bus master that is not said disconnected master attempts to access said first slave before the disconnected master retrieves data of said task from said first slave, said rerun command instructing said one of said at least one first bus master and said at least one second bus master to relinquish respectively a one of said first and second bus means and to attempt to access said first slave later, whereby transfer of data to an unintended master is prevented.

Claim 3

The bus-to-bus interface as set forth in claim 1, wherein said directory means further comprises busy indicator means for setting a busy flag when a particular master engages said first slave and issues an instruction resulting in said first slave issuing a rerun command.

Claim 4

The bus-to-bus interface as set forth in claim 2, wherein said directory means further comprises master identification means for identifying said particular master engaging said first slave.

Claim 5

The bus-to-bus interface as set forth in claim 3, wherein said busy indicator means further comprises first register means for storing a bit when said busy flag is set.

Claim 6

The bus-to-bus interface as set forth in claim 4, wherein said first register means comprises a plurality of first registers.

Claim 7

The bus-to-bus interface as set forth in claim 3, wherein said master identification means comprises second register means for storing a master identification tag identifying said particular master engaging said first slave.

Claim 8

The bus-to-bus interface as set forth in claim 6, wherein said second register means comprises a plurality of second registers.

Claim 9

The bus-to-bus interface as set forth in claim 7, wherein each of said second registers is associated with one of said first registers.

Claim 10

The bus-to-bus interface as set forth in claim 1, wherein said first bus means further comprises first bus master identification means.

Claim 11

The bus-to-bus interface set forth in claim 9, wherein said first bus masters are self-identifying.

Claim 12

The bus-to-bus interface as set forth in claim 1 further comprising means for second bus master identification.

Claim 13

The bus-to-bus interface as set forth in claim 1, wherein said rerun means issues only one rerun command.

Claim 14

The bus-to-bus interface as set forth in claim 1, wherein each of said slaves is identified by a block of address space.

Claim 15

The bus-to-bus interface as set forth in claim 1, wherein said slaves issue said rerun command.

Claim 16

In a multiple processor computer system having a first bus means and a second bus means, a bus-to-bus interface for coupling said first bus means to said second bus means such that data coherence is preserved, wherein said first bus means is coupled to at least one first bus master and operates according to a first protocol where each first bus master is self-identifying, and wherein said second bus means is coupled to at least one second bus master and a plurality of slaves and operates according to a second protocol where devices coupled to said second bus means are not self-identifying, said bus-to-bus interface comprising: protocol means including protocol conversion means coupled to said first and second bus means for permitting transfer of data between said first and second bus means and said slaves; busy indicator means, coupled to said first and second bus means, for maintaining a status for each of said plurality of slaves, for setting a busy flag when a first slave issues a first rerun command in response to said first slave accepting a command to perform a task from a first master, said first master being coupled to a one of said first bus means and said second bus means, said first rerun command causing said first master to relinquish said first and second bus means and to attempt to access said first slave later, said busy indicator means permitting only said first master to access said first master while said busy flag is set; master identification means coupled to said first and second bus means for identifying each of said first and second bus masters that engages one of said plurality of slaves, for generating a master identification tag identifying each of said first and second bus masters that engages a one of said plurality of slaves, and for storing each master identification tag; and rerun means coupled to said first and second bus means for issuing a second rerun command when a one of said first and second bus masters other than said first master attempts to access said first slave, said second rerun command causing said one of said first and second bus masters to relinquish said first and second bus means and to attempt to access said first slave later; said first master continuing to attempt to access said first slave and relinquishing said first and second bus means after receiving said first rerun command issued by said first slave until said first slave is no longer performing said task, said bus-to-bus interface permitting said first master to access said first slave and retrieve data after said first slave is no longer performing said task, whereby to prevent transfer of data to an unintended master.

Claim 17

In a multiple processor computer system having a first bus means and a second bus means, a bus-to-bus interface for coupling said first bus means to said second bus means such that data coherence is preserved, wherein said first bus means is coupled to at least one first bus master and operates according to a first protocol where each first bus master is self-identifying, and wherein said second bus means is coupled to at least one second bus master and a plurality of slaves and operates according to a second protocol where devices coupled to said second bus means are not self-identifying, said bus-to-bus interface comprising: protocol means including protocol conversion means coupled to said first and second bus means for permitting transfer of data between said first and second bus means and said slaves; busy indicator means, coupled to said first and second bus means, for maintaining a status for each of said plurality of slaves, for setting a busy flag when a first slave issues a first rerun command in response to said first slave accepting a command to perform a task from a first master, said first master being coupled to a one of said first bus means and said second bus means, said first rerun command causing said first master to relinquish said first and second bus means and to attempt to access said first slave later, said busy indicator means permitting only said first master to access said first master while said busy flag is set; master identification means coupled to said first and second bus means for identifying each of said first and second bus masters that engages one of said plurality of slaves, for generating a master identification tag identifying each of said first and second bus masters that engages a one of said plurality of slaves, and for storing each master identification tag; and rerun means coupled to said first and second bus means for issuing a second rerun command when a one of said first and second bus masters other than said first master attempts to access said first slave, said second rerun command causing said one of said first and second bus masters to relinquish said first and second bus means and to attempt to access said first slave later; said first master continuing to attempt to access said first slave and relinquishing said first and second bus means after receiving said first rerun command issued by said first slave until said first slave is no longer performing said task, said bus-to-bus interface permitting said first master to access said first slave and retrieve data after said first slave is no longer performing said task, whereby to prevent transfer of data to an unintended master.

Claim 18

The bus-to-bus interface as set forth in claim 15, wherein said busy indicator means comprises first register means including a plurality of first registers for storing, when said busy flag is set, a bit when said first slave is engaged.

Claim 19

The bus-to-bus interface as set forth in claim 16, wherein said master identification means comprises second register means including a plurality of second registers for storing said master identification tag corresponding to said first master engaging said first slave.

Claim 20

The bus-to-bus interface as set forth in claim 17, wherein said each of said second registers is associated with one of said first registers.

Claim 21

The bus-to-bus interface as set forth in claim 18, wherein said second register means stores said master identification tag in a particular second register when said busy flag is set.

Claim 22

The bus-to-bus interface as set forth in claim 15, wherein said first bus means further comprises first bus master identification means.

Claim 23

The bus-to-bus interface as set forth in claim 20, where said first bus masters are self-identifying.

Claim 24

The bus-to-bus interface as set forth in claim 15, wherein said bus-to-bus coupler further comprises second bus master identification means.

Claim 25

The bus-to-bus interface as set forth in claim 15, wherein said rerun means issues only one rerun command.

Claim 26

The bus-to-bus interface as set forth in claim 15, wherein said each of said first and second bus slaves is identified by a block of address space.

Claim 27

In a multiple processor computer system having a first bus means and a second bus means, a method for coupling said first bus means to said second bus means such that data coherence is preserved, wherein said first bus means is coupled to at least one first bus master and operates according to a first protocol where each first bus master is self-identifying, and wherein said second bus means is coupled to at least one second bus master and a plurality of slaves and operates according to a second protocol where devices coupled to said second bus means are not self-identifying, said method comprising the steps of: providing protocol means including protocol conversion means for permitting transfer of data between said first and second bus masters and said slaves; providing directory means for maintaining a status for each of said plurality of slaves, for determining that a first slave is performing a task for a disconnected master, said disconnected master being a bus master that is coupled to a one of said first bus means and said second bus means, said disconnected master having commanded the first slave to perform said task and subsequently relinquished said second bus means, the directory means for establishing an identity for said disconnected master and associating the identity of the disconnected master with the first slave such that only said disconnected master is permitted to access the first slave; and providing rerun means for issuing a rerun command when a one of said at least one first bus master and said at least one second bus master that is not said disconnected master attempts to access said first slave before the disconnected master retrieves data of said task from said first slave, said rerun command instructing said one of said at least one first bus master and said at least one second bus master to relinquish respectively a one of said first and second bus means and to attempt to access said first slave later, whereby transfer of data to an unintended master is prevented.

Claim 28

In a multiple processor computer system having a first bus means and a second bus means, a method for coupling said first bus means to said second bus means such that data coherence is preserved, wherein said first bus means is coupled to at least one first bus master and operates according to a first protocol where each first bus master is self-identifying, and wherein said second bus means is coupled to at least one second bus master and a plurality of slaves and operates according to a second protocol where devices coupled to said second bus means are not self-identifying, said method comprising the steps of: providing protocol means including protocol conversion means for permitting transfer of data between said first and second bus masters and said slaves; providing directory means for maintaining a status for each of said plurality of slaves, for determining that a first slave is performing a task for a disconnected master, said disconnected master being a bus master that is coupled to a one of said first bus means and said second bus means, said disconnected master having commanded the first slave to perform said task and subsequently relinquished said second bus means, the directory means for establishing an identity for said disconnected master and associating the identity of the disconnected master with the first slave such that only said disconnected master is permitted to access the first slave; and providing rerun means for issuing a rerun command when a one of said at least one first bus master and said at least one second bus master that is not said disconnected master attempts to access said first slave before the disconnected master retrieves data of said task from said first slave, said rerun command instructing said one of said at least one first bus master and said at least one second bus master to relinquish respectively a one of said first and second bus means and to attempt to access said first slave later, whereby transfer of data to an unintended master is prevented.

Claim 29

The method as set forth in claim 25, wherein providing said directory means further comprises providing busy indicator means for setting a busy flag when a particular master engages said first slave.

Claim 30

The method as set forth in claim 26, wherein providing said directory means further comprises providing master identification means for identifying said particular master engaging said first slave.

Claim 31

The method as set forth in claim 27 wherein providing said directory means further comprises providing first register means for storing a bit when said busy flag is set.

Claim 32

The method as set forth in claim 28, wherein said first register means comprises a plurality of first registers.

Claim 33

The method as set forth in claim 29, wherein providing said master identification means further comprises providing second register means for storing a master identification tag corresponding to said particular master engaging said first slave.

Claim 34

The method as set forth in claim 30, wherein said second register means comprises a plurality of second registers.

Claim 35

The method as set forth in claim 31, wherein each of said second registers is associated with one of said first registers.

Claim 36

The method as set forth in claim 25, wherein said first bus means further comprises first bus master identification means.

Claim 37

The method as set forth in claim 25 wherein said rerun means issues only one rerun command.

Claim 38

The method as set forth in claim 25, wherein said each of said slaves is identified by a block of address space.